Circuit protects bus from 5V swings

The circuit in Figure 1 automatically detects voltage and protects a bus, such as a 3.3V-limited PCI bus, from 5V signal-level swings. You can also use the circuit to determine bus-voltage swings within one bus-cycle for setting appropriate termination voltages of protection diodes or termination resistors. Today's deep-submicron VLSI-manufacturing techniques sometimes require circuits to limit I/O voltages to 3.3V signal swings. Connecting such circuits to a bus with 5V level-swing cards could damage the circuitry. The circuit in Figure 1 can accurately and—within one bus cycle—detect a level swing larger than 3.3V on any bus and, upon a fault situation, generate a reset signal and an alarm output to notify the user and the system of this fault. Some of the novel circuit features include a highly accurate synchronous-detection capability to avoid false alarms arising from large signal overshoots, high impedance and low capacitive loading of the bus, automatic system shutdown during fault conditions, and a single-cycle response time.

This circuit successfully operates in products using the high-performance 3.3V MAP-CA processor family from Equator Technologies (www.equator.com), but you can use it in other high-speed 3.3V or even lower voltage systems. Equator's latest generation chips are 5V-tolerant, but you can adjust the circuit to protect other 1.8 and 2.5V chips. The circuit uses IC₃, an ultrahigh-speed Maxim (www.maxim-ic.com) MAX999 comparator with 4.5-nsec propagation delay, T_PD, to constantly compare a signal line, PCI_AD10 in case of a PCI bus, to a reference level of 3.8V. This reference voltage is an optimal compromise between 5V signals clamped by 3.3V protection diodes and the normal-operation 3.3V signals. Once the voltage exceeds this reference level for an entire bus clock period, the system turns on an alarm buzzer connected to Q₁.

The circuit generates a signal that can reset the system, or it can generate a system-error signal. Because the alarm-register memory, IC_2B, serves as an asynchronous register, you can switch the alarm off only by removing power from the system or by asserting the reset signal. To avoid false triggering by signal overshoot and undershoot, a flip-flop-based register, IC_2A, samples the comparator output only during the rising edges of the bus clock. This method allows for a generous 33-nsec period at 33 MHz for the bus signal to settle down before being sampled. Lowpass filtering by sensor resistors R₂, R₃ and the 3- to 5-pF parasitic capacitance on Pin 3 of IC₃ limit the maximum clock speed of this circuit. The traces connecting to Pin 3 of IC₃, R₂, and R₃ thus must be as short as possible and may limit the bus speed to approximately 40 to 50 MHz. Symmetrically lowering the resistance of R₂ and R₃ increases the maximum bus speed to a theoretical 7-nsec cycle time (greater than 140 MHz) at the expense of a higher signal-loading current on the bus.

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