VCXO makes inexpensive dual-clock reference

This Design Idea describes an inexpensive circuit to generate two extremely high-quality, crystal-clock-reference-signals, one of which is a PWM-controlled VCXO (voltage-controlled crystal oscillator) clock signal (Figure 1). The design also includes circuitry to statically switch and hold the VCXO at its nominal fixed frequency of operation (equivalent to 50% PWM) without requiring any external PWM stimulus. Most digital audio/video microprocessor-based systems today require several independent clocks with low jitter and the potential adjustability a VCXO provides. The described circuit replaces two expensive monolithic VCXO and crystal oscillators at a fraction of their cost and provides much higher quality output signals than the monolithic solutions can generate, especially at the control limits of the VCXO (±100% deviation). The circuit generates signals with higher stability, much lower jitter, lower operating voltage (3.3 versus 5V) and a wider VCXO pull range than comparable monolithic approaches at less than one-third of their cost.

You can use the circuit in a wide variety of applications; the indicated component values make it a perfect fit for a digital audio/video system, such as a digital video recorder, digital camera, or set-top box. The circuit is well-suited to single-chip, media-processing applications that require adjustability, low cost, and low-jitter performance, such as systems based on Equator's (www.equator.com) broadband-signal processors. These types of systems generally require a fixed frequency, such as 25 or 33 MHz, for the processor subsystem (Ethernet, PCI bus, for example) and an adjustable 27-MHz reference clock for the audio/video reference subsystem. A PLL system generally controls the 27-MHz reference clock. (This PLL is usually implemented in software with PWM outputs from the microprocessor controlling the 27-MHz clock's deviation.) This approach guarantees a correct synchronization of the audio and the video data streams to each other and the broadcast source. The clock requires ±50-ppm adjustability, and the circuit in Figure 1 provides more than ±70 ppm. The circuit suits high-volume manufacturing, the highest quality signal (lowest jitter), and the lowest production cost.

The design incorporates several novel circuit features, such as both overtone- and harmonic-crystal operation, use of inexpensive voltage-controlled capacitors (varactor diodes), a single 3.3V power-supply operating voltage, and a selectable 50%-duty-cycle, 27-MHz-operation, fixed-frequency mode. The fixed-frequency mode allows operation at 27 MHz without the PLL-PWM circuit's having to provide a 50% duty cycle, potentially freeing up hardware and software resources in the microprocessor that usually generates the PWM signal. This mode is usually invoked when the audio/video signals are generated internally to the system, such as when playing back from a hard drive, and audio/video synchronization to an external source is unnecessary.

The circuit includes IC₁, a 32-MHz, PCI-based fixed-frequency reference clock; IC₂, a PWM multiplexer; and IC₃, a 27-MHz VCXO clock. A Fox (www.foxonline.com) 32-MHz, third-overtone crystal serves to generate both the PCI reference clock and the 50%-duty-cycle reference for the fixed-frequency mode. A third-overtone, 32-MHz part is less expensive and more mechanically robust than a 33-MHz, fundamental-mode crystal at the expense of running the PCI clock slightly slower. The tank circuit around inductor L₁ and capacitors C₁ and C₃ prevent the crystal from oscillating at its fundamental mode of approximately 11 MHz. This tank circuit works by creating an LC series-resonant circuit between L₁ and C₃ that has natural resonance at approximately 24 MHz, which is approximately 75% of the desired 32-MHz frequency. Note that C₁ is large enough to have no effect on this tank circuit's resonance frequency; it merely acts as a dc blocker for inductor L₁. One thing to avoid is to connect this tank circuit to the input side of inverter IC_1A. Connecting it to the input side of IC_1A could potentially create a resonant RC circuit with resistor R₁ and capacitor C₁ acting as the RC components. This circuit could oscillate at less than 1 kHz, a frequency at which L₁ would effectively be a short circuit, and crystal Y₁ would be an open circuit. Placing C₁ and L₁ on the output side of IC_1A prevents this spurious-oscillation mode.

Digital multiplexer IC₂ forwards one of two PWM signals to the VCXO based on the state of the fixed-versus-VCXO selected input signal. The PWM-input signal serves as the PWM reference input to the VCXO if the select pin is high, and the design uses the 50%-duty-cycle PWM signal from the PCI clock circuit if the select pin is low. The design uses a 74LVC00 chip as a multiplexer because of its ready availability and low cost. IC_2C buffers the PWM signal, and the cascaded RC filter comprising R₈, R₉, C₈, and C₉ then lowpass-filters the signal. The analog-voltage stability of the VCXO control voltage at the output of this RC filter depends on the quality of the V_DD supply to IC_2C. IC₂ receives its 3.3V power through an RC filter: R₄ with C₄ and C₅. IC₂ with R₈, R₉, C₈, and C₉ thus form a highly accurate D/A converter.

The VCXO's lowpass filter uses a cascaded design, because stray 32-MHz noise could pass across the small parasitic capacitance inherent in R₈ into the analog VCXO-control voltage. Cascading also has the advantage of filtering noise with 12 dB of attenuation per octave for frequencies greater than 5 kHz, thus creating a noise-free VCXO control voltage. The 27-MHz audio/video VCXO circuit uses a fundamental-mode crystal that varactor diodes D₁ and D₂ load with adjustable capacitance. These back-biased diodes' junction capacitance depends highly on the bias voltage. Larger bias voltages lower their capacitance, thus lowering the load across the crystal and increasing its oscillation frequency. Diodes D₁ and D₂ find use in many tuners and are widely available. Capacitors C₆ and C₇ again function as dc blockers.

The adjustment range of the VCXO is approximately 27 MHz ±2 kHz, which calculates to approximately ±74 ppm. The circuit is stable with very low jitter throughout its entire 0 to 100% VCXO-adjustment range. You can use the VCXO subcircuit by itself to generate a spread-spectrum clock for EMI compliance. You drive the VCXO voltage or PWM duty cycle from 0V (0%) to 3.3V (100%) with a triangular-shaped drive signal. The frequency of the triangular wave must be below the PWM RC filter's cutoff frequency of 24 Hz to be effective. The oscillator circuit's jitter depends on the power-supply quality of IC₁, IC₂, and IC₃ and on the noise inside these chips. To avoid crosstalk between 32 MHz and 27 MHz, the design uses two chips. Implementing buffers IC_1B and IC_3B with separate chips, thus separating the power-supply loading from the sensitive buffers, IC_1A and IC_3A, could further reduce jitter. With independent clock buffers and a low-noise power supply, this circuit has exhibited a maximum cycle-to-cycle jitter of less than the 60-psec limitation of the HP54720D oscilloscope that measures it. This figure betters the jitter characteristics of popular crystal oscillators and VCXO chips available for consumer applications. It also does not suffer from unstable operation at its adjustment margins (operating at ±100% deviation), as designers commonly encounter with monolithic components. Another added benefit is that it achieves its ±74-ppm adjustment range with only a single 3.3V power supply, whereas monolithic approaches usually require a 5V power supply and control voltage. Finally, it offers all this performance at a total price of less than $1.40 in large quantities by using only commonly available, off-the-shelf components. This figure compares to $3 to $6 parts cost with monolithic approaches.