The nuances of op-amp integrators

An integrator that you configure with an op amp is a simple circuit consisting of a resistor, a capacitor, and an op amp, so how can anything go wrong? In Figure 1, when Z_F is a capacitor, the closed-loop ideal-gain equation is G=–1/R_GCs, where s is the Laplace complex operator. Thus, the circuit performs a pure integration. Some designers mistakenly claim that this configuration can be unstable, so you can calculate the loop gain using Equation 1 to determine whether a potential stability problem exists.

EQUATION 1

where a is the op-amp open-loop gain.

On the well-known Bode plot, the zero contributes 90° positive phase shift starting at the lowest frequency axis, and the pole contributes –45° phase shift at the frequency at f=1/(2πR_GC). The total phase shift is 45° at f=1/(2πR_GC), and the phase shift decreases to zero at approximately 10f. The phase shift never comes close to the –180° required for instability, so the circuit problems must be elsewhere.

You can easily solve the saturation problem by adding a resistor in parallel with C; the resistor supplies the bias current, and saturation reduces to a small voltage offset. The closed-loop gain and loop-gain equations with the added parallel resistor follow:

EQUATION 2

and

EQUATION 3

You lose the pure integration with the addition of R_F. The circuit is an amplifier with an inverting gain of –R_F/R_G until the input frequency approaches f=1/(2πR_FC). Then, it acts as an integrator for higher frequencies, or a lowpass filter. The zero in the loop gain always precedes the pole in the frequency domain; thus, this circuit is always stable. Actually, you often add a feedback capacitor to an amplifier to reduce noise and overshoot.

A step-function input voltage causes an input current of V_IN/R_G, and the input current could damage the capacitor, damage the op amp, or cause ringing. Engineers often put a small resistor in series with the capacitor to improve reliability. The closed-loop gain and loop-gain equations with the added series resistor follow:

EQUATION 4

and

EQUATION 5

You regain the pure integration if R_GC is greater than R_FC, and this integration lasts almost until f=1/(2πR_FC). The loop gain has a zero, which contributes 90° positive phase shift at the low-frequency axis, so the pole usually can't cause instability. Situations might arise in which R_GC is less than R_FC and the circuit is unstable, but I've never seen this case.

Some final points to consider are:

• Nonrepetitive input signals require resetting the integrator by discharging C (FET in parallel with C),
• C is subject to dielectric stress that can cause a dual slope integration, and
• you must account for C's leakage current.

Inverting integrators are well-behaved circuits, but, like all analog circuits, they require attention to detail.