Sometimes, one capacitor is better than two
Robert LeBoeuf, National Semiconductor, Salem, NH -- 6/5/2000
Many A/D converters use an internal resistor ladder as a two-point
differential voltage reference in the conversion. This method demands that these
two nodes remain steady. The higher the resolution, the stronger the demand for
quiet voltages. Figure 1 depicts a simplified schematic of the LM985XX reference ladder. Figure 1a shows the traditional decoupling scheme; Figure 1b shows a
proposed scheme. Typically, designers use two capacitors to decouple each
reference node—one low-value capacitorand one of higher value because the
effective series inductance (ESL) of the smaller capacitor is much lower than
that of the larger one. Contrary to tradition, you can eliminate these larger
capacitors and replace them with one differential capacitor if you choose the
values wisely. Because the difference in the reference voltages,
VREF, is important in conversion, this is the delta that is of interest.Figure 1b shows two common-mode decoupling capacitors, C1 and C2, and the differential capacitor, C3. The current sources, I1 and I2, represent the average currents pushing or pulling on the ladder. These currents are generally proportional to the input voltage, VIN, and the sampling frequency, f. If the input voltage is periodic or at least quasiperiodic, then you can choose the decoupling capacitors on the basis of the maximum ripple voltage allowed to appear differentially on the nodes. This ripple specification is based on the permissible output error. The poles and zero of the transfer function are, respectively,


where k, n, and m are cyclic permutations of 1, 2, and 3. You can easily see that the pole in the first equation is the dominant pole. As long as the zero is sufficiently far from pole1, then this pole (hence, C3) determines the roll-off. If C1 and C2 are small enough, the zero finds itself well away from pole1. Using the values in Figure 1b, the poles and zero become pole1=–28.50 Hz; pole2=–3.948×104 Hz; and zero=2.48×105 Hz.
Typically, the current sources have a fundamental frequency equal to the frequency of the analog clamp. The most pessimistic assumption is that the input signal contains all white pixels. This scenario causes the maximum swing in the current sources and the smallest duty cycle. Using this assumption and a current amplitude of 0.6 mA, the capacitor values shown in Figure 1b would produce
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