Lithography simulator helps designers check integrity of OPC layouts

By Michael Santarini -- 5/23/2005

Photolithography-tool-vendor Sigma-C contends that your OPC (optical-proximity-corrected) design may not be correct at all. The Munich-based vendor has expanded into the design-for-manufacturing tool market with the new Solid+ microlithography simulator that lets IC designers know whether photoresist equipment can accurately print their OPC-IC layouts. Sigma-C based the new tool on its Solid line of lithography-optimization tools. Those tools draw on a database that characterizes equipment, materials, and processes and helps lithography engineers simulate and derive manufacturing processes.

The company will show Solid+ next month at the Design Automation Conference in Anaheim, CA. The tool uses the same database and lithography models as Solid to ensure that simulations accurately correlate with the process. However, Solid+ targets chip and cell designers and allows them to tell during chip and cell development whether their designs and OPC and ORC (optical-rule-checking) tools are process-accurate, says Thomas Blaesi, vice president marketing and business development.

Peter Feist, Sigma-C’s chief operating officer, explains that, at the 90-nm node, OPC becomes a must at all layers and that the 65-nm node is taxing for traditional OPC and ORC tools. To ensure OPC layouts are process-accurate requires simulation with Solid+. “Sigma-C’s goal is to help the semiconductor industry bridge the gap between design and printed-wafer results and ultimately prevent mask failure at 65 nm and below,” he says.

“A lot of masks are failing because models used in OPC are inaccurate,” says Blaesi. “We reproduce the real expected pattern on the wafer. Solid+ lets design engineers verify their patterns at these smaller process nodes, which masks can then accurately reproduce.”

The 3-D technology uses an analytical-resist, rather than a numerical, model like competing OPC tools and thus has Spicelike accuracy with the ability to simulate aerial images to the macro level and resists image to the cell level. The tool’s engine simulates cells as large as 100×100 microns. “There is an opportunity to become the golden tool in the industry to help other tools calibrate their models,” Blaesi says. Users will feed the tool GDSII files, and the tool exports resist profiles in a GDSII layer with defect information.

The initial release forces users to manually adjust OPC models and layouts, but a lot of opportunities exist to automate that process, according to Blaesi. Solid+ and Solid both use the same database and same manufacturing models, which allows manufacturing to share up-to-date process information with designers targeting their designs at an evolving process. In offering Solid line of lithography tools over the last 10 years, the company also has established relationships with IC-mask makers, manufacturing-equipment makers, foundries, and semiconductor vendors. The company expects to have the technology ready for commercial use in the fourth quarter of this year.

Sigma-C, www.sigma-c.com.

 

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