CMOS inverters convert RF to digital signal

Applications ranging from frequency counting and synthesis to sensor signal conditioning require conversion of RF signals to digital-logic levels. In such situations, designers typically use a high-speed voltage comparator to perform the RF-to-digital conversion. Due to their high gain, voltage comparators typically exhibit good sensitivity but also present some drawbacks. High-speed comparators are expensive, difficult to find off the shelf, and prone to rapid obsolescence.

For frequencies as high as 180 MHz, the circuit in Figure 1 offers an attractive approach. The IC in the design, a 74LVCU04 very-high-speed CMOS hex inverter, is available off the shelf and from many sources. Furthermore, many applications may already include three unused inverters. A single inverter, IC_1A, operating as a linear preamplifier, forms the converter's input stage. Biasing resistor R₃forces the inverter into its linear region by equalizing its input and output voltages at one-half of the power-supply voltage, V_O1=V_I1=(V_DD/2). Because the ac gain of a very-high-speed CMOS inverter is relatively low at RF (V_O1/ V_I1)≈7, additional gain stages follow the preamplifier. One self-evident approach—a cascade of additional inverters—presents poor stability at low frequencies and at dc when no RF source is present.

The circuit in Figure 1 eliminates this drawback thanks to a topology based on a Schmitt trigger and amplifier circuit, IC_1B and IC_1C, that includes a frequency-dependent positive-feedback network comprising R₁, R₂, C_D1, and C_D2. Depending on the input frequency, the network exhibits two behaviors: At high frequencies, the decoupling-capacitor pair, C_DC1 and C_DC2, short-circuits feedback resistor R₁, canceling the time constant introduced by the positive-feedback network, R₁ and R₂, and the input capacitance of inverter IC_1B. Consequently, at high frequencies, the three inverters, IC_1A, IC_1B, and IC_1C, behave as three cascaded, high-speed amplifiers that allow the best performance in input-signal bandwidth. At dc and low frequencies, the influence of coupling-capacitor pairs C_D1and C_D2 is negligible, and inverters IC_1B and IC_1C and the positive-feedback network, R₁and R₂, act as a Schmitt-trigger circuit. The choice of the high- and low-threshold voltages, V_THand V_TL, at the Schmitt trigger's input, V_O1, stems from a compromise between input sensitivity at V_S and ensuring unconditional stability of the comparator's output. Equations 1 and 2 set the high and low threshold voltages, respectively:

   (1)

     (2)

Knowing that

   (3)

with Z_C=50Ω, you can use the data in Figure 2 to extract the first inverter's input impedance at the frequency of interest. At 150 MHz, this yields Z_I1= 106.1Ω–j 116.7Ω (at Marker 4 in Figure 2 ). To determine values for the matching network's components, you can use any of several software tools (references 1 and 2). If you are unfamiliar with Smith-chart computations, you can also proceed analytically with the following method:

1. Use series-to-parallel transformation formulas (equations 4and 5) to transform the first inverter's input impedance into a parallel form:

   (4)

   (5)

Applying these formulas at 150 MHz yields: R_P=233Ω, and X_P=213Ω. (At 150 MHz, X_Prepresents an input capacitance, C_P=5 pF.)

2. Compute an initial version of the matching network to perform a match between the real part of the first inverter's input impedance, R_P, and the 50Ω RF source. Solving equations 6 and 7 yields values for the matching network's elements (Reference 3):

   (6)

   (7)

Applying these formulas at 150 MHz yields L₁≈100 nH, and C₁ +C_P≈8.7 pF.

3. Subtract the inverter's input capacitance, C_P =5 pF, from Equation 7 to calculate a value for C₁:

   (8)

To build the circuit, use standard component values that fall closest to the computed values: L₁=100 nH, and C₁=3.6 pF. As the plot of input frequency versus sensitivity in Figure 3 shows, the circuit's increased sensitivity for 100- to 170-MHz frequencies clearly demonstrates the impedance-matching network's effectiveness. You can optimize the circuit's sensitivity in any other frequency band of interest by applying this method at the chosen frequency. The RF-to-digital-logic converter's power consumption does not change significantly for input signals of 10 to 180 MHz. Under worst-case conditions, the current drain does not exceed 58 mA for a supply voltage of 3.3V.