SOI emerges as bulk-CMOS alternative

By Ron Wilson, Executive Editor -- 3/17/2006

For CMOS logic, SOI (silicon-on-insulator) technology offers significant advantages over bulk silicon at the same geometry. Manufacturers have demonstrated those advantages using device-level parameters, such as active power, drive current, switching speed, and substrate coupling. SOI also offers some serious problems, again at the device level.

Design teams that have used SOI to date have done their own extensive process and device modeling. They have also built their own libraries and, often, their own design-tool chains to work with the foibles of the process. The most notable of these foibles is the “floating-body” effect, which causes the switching speed of an SOI transistor to depend on its recent switching history. That scenario can be less than ideal for timing closure.

But this year may see the opening of SOI to a broader audience Officials at physical-library developer Soisic believe that 2006 will see a number of major announcements of SOI SOCs (systems on chips) from fabless COT (customer-owned-tooling)-design teams. Soisic has enabled this change by producing and verifying logic libraries and memory compilers in SOI for a number of 90-nm foundry processes, according to Chief Executive Officer Eduard Weischselbaumer. These efforts should become public this year in process-design-kit announcements.

Physical libraries will bridge the gap between the device and netlist levels, enabling ordinary design teams to do what huge design teams that can spend two years modeling and building libraries can do. The key, according to Weischselbaumer, is that library designers must simultaneously provide the benefits and hide the complexities of SOI. By cleverly building the logic cells in its library, Soisic hides the SOI variation in switching speed from designers, so that library user must deal with only minimum and maximum delay values, as in any other CMOS process.

SOI design preserves the “variable-threshold” effect, which is the key benefit of CMOS processes. Because of the various coupling paths in an SOI transistor, the threshold voltage of the device drops significantly during a switching event. This decrease both improves the switching speed and increases the drive current. However, after the transition, the threshold returns to normal. In other words, a properly used, small-geometry SOI transistor can exhibit both a low threshold voltage for speed and a high threshold voltage for low subthreshold-leakage current. Achieving this benefit requires no back bias, power gating, or other dynamic-leakage-control techniques. So, through clever design, Soisic’s logic libraries and memory cells are both faster and lower in both active and leakage power than their bulk-CMOS counterparts, according to the company. And, like the bulk-CMOS libraries, the SOI libraries can provide either maximum performance or low power. By concealing the variable-delay effects and threshold variations inside the libraries, Soisic makes the libraries compatible with other tools and flows.

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