Zigbee chip project offers SOC challenges

By Ron Wilson, Executive Editor -- 4/17/2006

ZMD America's announcement of a single-chip, sub-1-GHz Zigbee interface for sensor-network applications may have made a significant ripple in the increasingly active Zigbee pond. But it also provides an interesting window into how the SOC (system on chip) design process grows rapidly more complex with the addition of RF blocks to the architecture.

ZMD, a 45-year-old company based in Dresden, Germany, is no stranger to mixed-signal and RF design—a fact that may have made the current chip feasible. Rather than start with a clean sheet of paper and design a radio, controller state machines, and a MAC (media access controller) from scratch, the company decided to use a combination of internally developed and third-party blocks and to use a block-integration methodology. This might be an obvious choice for a purely digital SOC, but it is a bold approach for an RF SOC.

The process began with some hard partitioning decisions, according to Kory Brown, ZMD's vice president for wireless products. Earlier entrants in the Zigbee race had offered bare radio chips without MACs or protocol controllers. This made the design relatively easy for the vendor, but it complicated things considerably for the user, who had to understand the topologies of Zigbee networks—there are three—and the access protocols, along with the higher layers of the stack.

On the other hand, integrating too much into a single chip would both narrow the market (by offending prospects with their own religious beliefs about microcontrollers and software stacks) and drop a significant new noise source (a microcontroller core) onto the die. Given these considerations, ZMD opted for a physical-layer radio with what the company calls a "thin" MAC. The device has no on-chip microcontroller core, but does provide sufficient state machines that the chip can by itself handle such frequent or time-critical functions as autoacknowledge, wake up, and beacon generation (click here for a data sheet including a block diagram). Software running on the user's choice of microcontroller handles the rest of the MAC layer and the higher layers of the protocol. ZMD has formed partnerships with several software suppliers to provide this functionality.

Power management played a driving role in partitioning the design. ZMD architects worked through the various operating modes that the different Zigbee network topologies impose on the radio and MAC and attempted to partition the chip so that as few blocks would be active as necessary in any given mode. They identified three primary operating modes: a roughly 30-mA transmit/receive mode with a very low duty cycle; a frequently-used idle mode that draws about 1 mA and requires about a microsecond to wake up the chip; and a deeper sleep mode in which only critical state machines are operating, drawing about 2.5 µA. A shutdown mode draws under 1 µA.

The engineers implemented the intermediate modes, such as idle, with a certain amount of clock gating, Brown says, but accomplished much of the savings by simply turning off power domains. This led to isolated power domains for the digital logic, the critical PLL (phase-locked loop), and the remaining analog functions.

Once the architecture was in place, the team began block selection and integration. The company decided to license a PLL from an IP company in Spain, but that turned out to be less than a turnkey solution. In the end, the team was able to use the internal architecture of the PLL and benefited considerably from working with the designers during verification, Brown says. However, tweaking the part to ZMD's requirements and integrating it required about a year of ZMD design time.

Meanwhile, the overall chip design began life as a Matlab model. The team used the model to create detailed definitions of the boundary conditions for each of the analog blocks—250 pages in all. These in turn went to analog design teams at various ZMD sites.

The dispersed teams joined a phone conference every morning and a video conference once a week. As the blocks began to emerge into simulation, the designers fed detailed performance figures back into the global chip model and repeated simulation. As the digital functionality began to emerge, the design moved from a pure Matlab representation to a mixed-signal behavioral model.

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The intimate connection between the digital and analog blocks in part drove the move to this behavioral model. In order to minimize power while maintaining an adequate bit error rate, the radio uses both digital spreading and pulse shaping and a programmable-gain linear power amplifier. Gain adjusts digitally in response to current network characteristics, using both a large-signal control with 7-dBm steps and a Vernier adjustment with much finer steps.

The company taped out the design for TSMC's quarter-micron CMOS process, a conservative choice entirely in line with the chip's performance and cost objectives. The die is relatively small, reducing the attractiveness of deep-submicron processes. Stability also factored into the choice. "We surveyed libraries and models for a number of process options," Brown says. "We found that at the time the inductor models for the TSMC process were weak, and we would have to do our own. But the rest of the models were quite usable. I understand they have released new inductor models as well now, but they weren't available during our design."

The aggressive specs for the completed chip, including –98 dBm sensitivity, suggest that design team's work on front-end partitioning, continuous remodeling of the design, and coordination between the design teams paid off. Also worth pondering is the side observation that a third-party IP supplier may be as valuable for its assistance during verification as for its IP.

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