Charge your SAR-converter inputs

It is tempting to drive a SAR (successive-approximation register) ADC with just an amplifier. As an added benefit, you might try to configure the amplifier circuit in a gain or antialiasing-filter stage. These enhancements seem reasonable as you try to optimize your device use. However, did you think about whether you would compromise the effectiveness of your op-amp/converter pair (Figure 1)?

If you need good, accurate performance at dc as well as ac, regardless of your throughput rate, the analog-input stage of the SAR ADC requires special attention. The model of the input stage of most modern ADCs is a resistor/capacitor pair with two switches and a voltage source (Figure 2). The resistance, R_SW, in the converter's input is the closed-switch resistance. This switch closes during the acquisition time of the conversion process and opens during the conversion time. The converter uses capacitance, C_SH, which is the total of the distributed on-chip capacitance, for the input-signal-sampling process.

First and foremost, you need to give sample capacitor C_SH enough charging time to reach at least  ½LSB of the final value. Theoretically, for a 12-bit converter, enough time would be more than eight times R_SW×C_SH. Given error margins and component variations, you should use multiples of 10 to 15. The SAR converter needs an op amp with a gain of ±1V/V, along with an R_IN–C_IN external resistor/capacitor pair. During sampling, the ADC uses capacitor C_IN for signal stability. Resistor R_IN isolates the amplifier from the ADC's load capacitance. The op amp isolates the ADC from high-impedance loads and drives C_IN and C_SH, facilitating a quick charge time while the ADC is sampling.