Panel probes future of design-for-test

By Ron Wilson, Executive Editor -- 5/3/2006

A blue-ribbon panel at the 2006 VLSI Test Symposium in Berkeley, CA, ran deep into the night Monday exploring the future of design for testability (DFT). The primary question was whether, in the face of the enormous challenges facing DFT engineers, point tools or integrated DFT environments are the answer. The panel's nearly unanimous answer: "Yes."

All the panelists agreed, in one way or another, that integration is absolutely essential, in two quite different respects. First and most obviously, DFT tools have to be able to exchange data with other design tools. "This industry started as a collection of point tools," observed Sanjiv Taneja, vice president for the Encounter Test product line at Cadence. "We then evolved into an architecture of tools—an architecture very much mirroring the architecture of the systems-on-chip we were designing."

The increasing complexity of the designs drove this integration, and in turn forced DFT tools to link to a broader array of other flows. For example, Taneja cited a study by STARC, the Japanese research consortium, showing that test escapes decreased significantly when engineers considered both timing and timing margin data for individual nets during the design of the test structures. This implies a need for a strong link between timing analysis and DFT.

Similarly, recent disasters have shown that DFT tools must be linked to power and voltage-drop analysis. "We need for the DFT flow to understand new issues, such as the need for scan chains to cross voltage domains on the chip," said Synopsys fellow Tom Williams. Others mentioned cases in which errors in the scan chains themselves rendered the DFT design useless.

Further, test must link to failure analysis, with a feedback path directly into the design team. "Pass/fail diagnostics are insufficient today," stated Robert Hum, general manager and vice president for design verification and test for Mentor Graphics. "New chips must ramp into full production so quickly, and have such short product lives, that we have to learn from every test reject. We can't just find the first failure and toss the part. We have to push on, to find all the failures on each chip and diagnose each one. And then we have to get that data back to the design team as quickly as possible."

Several panelists raised the issue of the growing reuse of intellectual property (IP) in chip design. On one hand, the value of IP is that it requires—in principle—no internal design work, only integration into the larger chip design. On the other hand, unless the DFT provisions within the IP both provide adequate coverage and have an architecture that integrates well into the overall chip DFT architecture, trouble will result. "DFT must start with the IP blocks," said Syntest president and CEO LT Wang.

Yes, IP must carry its own DFT with it, argued Yervant Zorian, vice president and chief scientist at Virage Logic. "Specialized DFT IP is now incorporated within IP cores," he said. "This has to be the case because in many situations only the IP designers have enough knowledge of the core to provide the correct test, diagnosis, and in some cases repair IP for it." Hence another domain across which the DFT effort must be integrated.

Reaching beyond the design team in another direction, panelists pointed out that DFT must be integrated as well with the work of ATE (automated test equipment) designers. Only DFT architectures working in concert with ATE architectures can provide the combination of coverage, mixed-mode test, and test time customers demand.

Beyond ATE waits another frontier as well. Several panelists mentioned, tentatively, a necessary link between DFT and the emerging DFM (design-for-manufacturing) discipline. DFM may be necessary to inform the DFT architecture what to look for, they hinted. And diagnostics based on DFT may be necessary to tune DFM tools in order to improve yields.

Finally, the panelists agreed that customer demands will drive this integration. On their own, neither IP vendors nor EDA companies nor even foundries will have the will and leverage to bring about an integrated framework in which major DFT packages interoperate with the latest and hottest point tools. But major customers, leaning on all these parties, could make it happen. "Change comes from the customer with a financial stake in the results," Hum stated.

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