Load-transient-response testing for voltage regulators

Semiconductor memory, card readers, microprocessors, disk drives, piezoelectric devices, and digital systems create transient loads that voltage regulators must service. Ideally, regulator output would be invariant during a load transient. In practice, however, some variation occurs, and this variation becomes problematic if a system exceeds its allowable operating-voltage tolerances. This problem mandates testing the regulator and its associated support components to verify desired performance under transient-loading conditions. You can use various methods to generate transient loads and allow observation of regulator response.

Figure 1 shows a conceptual load-transient generator. The regulator under test drives dc and switched resistive loads, which may be manually variable. The device monitors its switched current and output voltage, permitting comparison of the output voltage and the load current under static and dynamic conditions. The switched current is either on or off; there is no electronically controllable linear region.

Figure 2 shows a practical implementation of the load-transient generator. Capacitors augment the voltage regulator under test; these capacitors provide an energy reservoir, similar to a mechanical flywheel, to aid transient response. The size, dielectric, and location of these capacitors, particularly C_OUT, have a pronounced effect on transient response and overall regulator stability (reference 1 and reference 2). The input pulse triggers the LTC1693 FET driver to switch Q₁, generating a transient-load current from the regulator. An oscilloscope monitors the instantaneous load voltage and, through a "clip-on" wideband- probe, current (see sidebar "Probing considerations for load-transient-response measurements"). Figure 3 provides an evaluation of the circuit's load-transient-generating capabilities by substituting a low-impedance power source for the regulator. The combination of a high-capacity power supply, low-impedance connections, and generous bypassing maintains low impedance across frequency. Figure 4 shows the circuit in Figure 3's response to the LTC1693-1 FET driver (Trace A) by cleanly switching 1A in 15 nsec (Trace B). Such speed is useful for simulating many loads but has restricted versatility. Although fast, the circuit cannot emulate loads between the minimum and the maximum currents.

Figure 5's conceptual closed-loop load-transient generator linearly controls Q₁'s gate voltage to set instantaneous transient current at any desired point, allowing simulation of nearly any load profile. Feedback from Q₁'s source to the A₁ control amplifier closes a loop around Q₁, stabilizing its operating point. Q₁'s current assumes a value that depends on the control- input voltage and the current-sense resistor over a wide bandwidth. Once A₁ biases to Q₁'s conductance threshold, small variations in A₁'s output result in large current changes in Q₁'s channel. As such, A₁ need not output large excursions; its small signal bandwidth, rather than its slew rate, is the fundamental speed limitation. Within this restriction, Q₁'s current waveform is the same shape as A₁'s control-input voltage, allowing linear control of load current. This versatile capability permits a variety of simulated loads.

The circuit in Figure 8 considerably simplifies the previous circuit's loop dynamics and eliminates all ac trims. The major trade-off is a halving of speed. The circuit is similar to the one in Figure 6, except that Q₁ is a bipolar transistor. The bipolar's greatly reduced input capacitance allows A₁ to drive a more benign load. This approach permits you to use an amplifier with lower output current and eliminates the dynamic trims necessary to accommodate Figure 6's FET-gate capacitance. The sole trim is the 1-mV adjustment, which you accomplish as described. You can eliminate this trim at the cost of circuit complexity (see sidebar "A trimless, closed-loop-transient-load tester"). Aside from the twofold speed decrease, the bipolar transistor also introduces a 1% output-current error due to its base current. You add Q₂ to prevent excessive Q₁ base current when the regulator supply is absent. The diode prevents reverse-base bias under any circumstances.

Figure 9 and figure 10 show the two wideband circuits' operation. The FET-based circuit (Figure 9) requires only a 50-mV A₁ swing (Trace A) to enforce Trace B's flat-topped current pulse with 50-nsec edges through Q₁. Figure 10 details the bipolar-transistor-based circuit's performance. Trace A, taken at Q₁'s base, rises less than 100 mV, causing Trace B's clean, 1A current conduction through Q₁. This circuit's 100-nsec edges, about two times slower than the more complex FET-based version, are still fast enough for most practical transient-load testing.

These circuits permit rapid and thorough voltage-regulator load-transient testing. Figure 11 uses Figure 6's circuit to evaluate an LT1963A linear regulator. Figure 12 shows regulator response (Trace B) to Trace A's asymmetrically edged input pulse. The ramped leading edge, within the LT1963A's bandwidth, results in Trace B's smooth 10-mV p-p excursion. The fast trailing edge, well outside the LT1963A's passband, causes Trace B's abrupt disruption. C_OUT supplies too little current to maintain output level, and a 75-mV-p-p spike results before the regulator resumes control. In Figure 13, a 500-mA p-p, 500-kHz noise load, emulating a multitude of incoherent loads, feeds the regulator in Trace A. This frequency is within the regulator's bandwidth, and only 6 mV p-p of disturbance appears in Trace B, the regulator output. Figure 14 maintains the same conditions, except that noise bandwidth increases to 5 MHz. This increase exceeds regulation bandwidth, resulting in more than 50-mV p-p error, an eightfold increase.

Figure 15 shows what happens when you present a 0.2A, dc-biased, swept, dc to 5-MHz, 0.35A load to the regulator. The regulator's rising output impedance versus frequency results in ascending error as frequency scales. This information allows determination of regulator output impedance versus frequency.

The regulator employs capacitors at its input (C_IN) and output (C_OUT) to augment its high-frequency response. You should carefully consider the capacitor's dielectric, value, and location because they greatly influence regulator characteristics (reference 1, reference 2, and reference 3). C_OUT dominates the regulator's dynamic response; C_IN is much less critical, as long as it does not discharge below the regulator's dropout point. Figure 16 shows a typical regulator circuit and emphasizes C_OUT and its parasitics. Parasitic inductance and resistance limit capacitor effectiveness at frequency. The capacitor's dielectric and value significantly influence load-step response. A "hidden" parasitic, impedance buildup in regulator-output-trace runs, also influences regulation characteristics, although you can minimize the parasitic's effects by remote sensing and distributed capacitive bypassing.

Figure 17 shows Figure 16's circuit responding (Trace B) to a 0.5A load step biased on 0.1A dc (Trace A) with C_IN=C_OUT=10 µF. The circuit employs low-loss capacitors, resulting in Trace B's well-controlled output. Figure 18 greatly expands the horizontal time scale to investigate high-frequency behavior. Regulator-output deviation (Trace B) is smooth with no abrupt discontinuities. Figure 19 runs the same test as Figure 17 using an output capacitor claimed as "equivalent" to the one that Figure 17 employs. At 10 µsec/division, the scope photos seem similar, but Figure 20 indicates problems. This photo, taken at the same higher sweep speed as the one in Figure 18, reveals the "equivalent" capacitor to have twice as much amplitude error, higher frequency content, and higher resonances than the one in Figure 18. (Always specify components according to observed performance, rather than salesmen's claims.) Figure 21 substitutes a lossy 10-µF unit for C_OUT. This capacitor allows a 400-mV excursion (note Trace B's vertical-scale change), greater than four times Figure 18's amount. Conversely, Figure 22 increases C_OUT to a low-loss, 33-µF type, decreasing Trace B's output-response transient by 40% versus Figure 18. Figure 23's further increase, to a low-loss, 330-µF capacitor, keeps transients inside 20 mV: four times lower than Figure 18's 10-µF value.

The lesson is clear: Capacitor value and dielectric quality have a pronounced effect on transient-load response. Try before specifying!

The closed-loop-load-transient generator also allows investigating load-transient rise time on regulation at high speed. Figure 24 shows Figure 16's circuit (C_IN=C_OUT=10 µF), responding to a 0.5A, 100-nsec rise-time step on a 0.1A dc load (Trace A). Response decay (Trace B) peaks at 75 mV with some following aberrations. Decreasing Trace A's load-step rise time (Figure 25) almost doubles Trace B's response error, with attendant enlarged following aberrations. This scenario indicates increased regulator error at higher frequency.

All regulators present increasing error with frequency—some more than others. A slow load transient can unfairly make a poor regulator look good. Transient-load testing that does not indicate some response outside regulator bandwidth is suspect.

The Intel embedded-memory voltage regulator furnishes a good, practical example of the importance of voltage-regulator-load-step performance. The memory requires a 1.8V supply, typically regulated down from 3V. Although current requirements are relatively modest, supply tolerances are tight. Table 1 shows only 0.1V allowable excursion from 1.8V, including all dc and dynamic errors. The LTC1844-1.8 regulator has a 1.75% initial tolerance at 31.5 mV, leaving only a 68.5-mV dynamic-error allowance. Figure 26 shows the test circuit. Memory-control-line movement causes 50-mA load transients, necessitating attention to capacitor selection. (The LTC1844-1.8's noise-bypass pin works with an optional external capacitor to achieve low output noise. This application, however, does not require it, and remains unconnected.) If the regulator is close to the power source, C_IN is optional. If not, use a high-grade, 1-µF capacitor for C_IN. C_OUT is a low-loss, 1-µF type. In all other respects, the circuit appears deceptively routine. A load-transient generator provides Figure 27's output-load test step (Trace A). This test uses Figure 8's circuit and changes Q₁'s emitter-current shunt to 1Ω. Trace B's regulator response shows just 30-mV peaks, more than two times better than necessary. Increasing C_OUT to 10 µF (Figure 28) reduces peak output error to 12 mV, almost six times better than specification. However, a low-grade 10-µF—or 1-µF, for that matter—capacitor produces Figure 29's unwelcome surprise. Severe peaking error on both edges occurs with 100 mV observable on the negative-going edge. (The photograph shows an intensified version of Trace B's latter portion to aid clarity.) This figure is well outside the error budget and would cause unreliable memory operation (reference 4, reference 5, and reference 6).