Intel Counters AMD's Torrenza
By Jessica Davis -- 9/28/2006
SAN FRANCISCO - Intel took square aim at rival Advanced Micro Devices' Torrenza socket strategy at IDF Wednesday, with a two pronged strategy designed to reduce bus bottlenecks, making it easier for other chips to work with Intel processors.
The world's largest chipmaker offered details about the strategy during keynotes and briefings at the Intel Developer Forum here this week.
The first part of the strategy allows programmable logic providers Xilinx and Altera to plug into Intel’s Front Side Bus. This approach allows the FPGAs (field programmable gate arrays) from those companies to be used as co-processor accelerators.
AMD’s HyperTransport bus is viewed has having a much lower latency than PCI Express, an interconnect standard championed by Intel, particularly for certain co-processing tasks.
“Today Hypertransport is better for fine-grained co-processing tasks,” said Misha Burich, senior VP of software and system engineering at Altera. Fine-grained tasks include floating point operations, while coarse-grained tasks include things like graphics coprocessing performed by devices such as those from Nvidia and ATI. The difference is not as pronounced with coarse-grained tasks.
Burich said that with the rise of large data centers driven by Web 2.0, using accelerators can help reduce power consumption and save energy. By allowing computation to be performed faster, Altera said that it has been able to achieve 30 percent to 50 percent reduction in system power requirements.
Xilinx also is seeing a growing market for FPGAs as accelerators.
“We see a growing interest,” said Ivo Bolsens, CTO at Xilinx. “Everywhere data centers are struggling with space and power issues.”
Bolsens said that Intel’s Geneseo is designed to improve issues of latency, bandwidth and cache coherency with PCI Express.
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