65-nm FPGAs consume less power
By Michael Santarini, Senior Editor -- 11/9/2006
Altera Corp has announced the new high-end Stratix III FPGA, the company's first in 65-nm process technology, claiming advances in power, performance, productivity, and price over its 90-nm FPGAs. According to Dave Greenfield, senior director of product marketing for high-end FPGAs at Altera, the company is increasing the number of logic elements from 180,000 to 340,000, the amount of memory from 8 to 17 Mbits, and the number of 18×18-bit DSP multipliers on board. Altera, like its archrival Xilinx with Virtex-5, has made power saving a top priority in developing its new 65-nm FPGA family, the Stratix III (see "FPGAs balance lower power, smaller nodes drip by drip," EDN, June 8, 2006).
Large, SRAM-based FPGAs have traditionally been power hogs, because all the transistors on a device consume power, even if the design layout doesn't use those transistors. Also, 65-nm processes inherently have more leakage than 90-nm processes because the increase in ever-thinner oxide transistors results in more static-power losses. To save power with its 90-nm Stratix II devices, Altera a few years ago made an eight-ALM (adaptive-logic module) the centerpiece of its Stratix II devices. Each FPGA contained tens of thousands of ALMs. A single ALM could locally perform computation rather than accessing data in disparate and distant parts of the FPGA. Thus, ALM-based architectures consume less power than traditional architectures.
With the new Stratix III, says Greenfield, Altera stayed with the eight-ALM structure but kept power on par with its 90-nm devices by employing other architectural improvements. One way that the company saved power is by creating configurable-logic elements that designers can choose to be either high-performance and low-power-consuming or low-performance and consuming half the power of Stratix II devices, depending on their targeted application.
Altera performed a study on 71 customer designs. The study indicates that, even in designs that customers consider high-performance applications, only about 15% of the logic on those designs on average require high-performance logic elements. The remaining 85% of the logic on those designs thus require no high-performance logic elements. Therefore, if designers can power down a large percentage of the logic of their designs, they can significantly cut overall power consumption.
The Stratix III manufacturing at TSMC incorporates all-copper routing; low-K dielectrics; strained silicon; and triple oxide, which helps stabilize power savings during the process reduction. The new devices operate an average of 25% faster than Stratix II devices and have a top clock speed of 600 MHz. Stratix III can also now support DDR3 and QDR+ high-speed interfaces at clock rates of 400 MHz, which Stratix II does not support. Stratix III also supports interfaces for DDR, DDR2, SDRAM, RLDRAM (reduced-latency DRAM) II, QDR II, and SRAM on as many as 24 modular I/O banks—all at higher clock rates than those of Stratix II.
Stratix III also has double the capacity of the Stratix II devices. The highest end Stratix III FPGA has 330,000 logic elements, which means designers can now use Altera FPGAs to serve as the heart of a system, instead of just using them for glue and control logic or to control datapath circuitry, says Greenfield. Because the devices are now so large, it is more than likely that it will now take a full design group to program one of the large devices. Therefore, the company has put greater emphasis on adding more team-based-design features and automation to its latest upgrade of Quartus II software, Version 6.1, to make designers more productive. The latest version includes multiprocessor support, detachable windows support, a chip planner, advanced I/O timing, and pin-planning enhancements. Altera now offers a Windows 64-bit version of Quartus II 6.1 as well as expanded Linux support for SUSE (Gesellschaft für Software und Systementwicklung MBH) Linux Enterprise 9 as well as Red Hat Enterprise. Prices for the 142000-logic-element EP3SL150, will start at $550 (1000). The company expects volume production to begin in 2008.
As with Stratix II, the company plans to offer Stratix III in three families: the Stratix III L logic-enhanced family; the Stratix III E family with enhanced memory and DSP functions for memory- and DSP-intensive applications; and the Stratix III GX family for transceiver applications. Altera will also offer a Hard Copy-structured ASIC variant.
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