Blaze DFM's dummy-fill-synthesis tool has smarts

By Michael Santarini, Senior Editor -- 12/14/2006

Blaze DFM is following up its mid-2006 release of its Blaze MO gate-CD biasing/leakage control tool with a dummy fill "synthesis" tool. The tool addresses the problems that IC foundries encounter when they apply CMP (chemical mechanical polishing). Foundries apply CMP to each metal, via, and active polysilicon layer of a wafer to remove irregularities on the surface of each IC layer and to ensure that the layers have a smooth surface. But, in finer process geometries, CMP often errantly creates its own topographical variations—nonuniform layers, or "dishing"—causing the features to work improperly. The CMP process can sometimes scrape away too much metal or distort features, causing electromigration or shorts. All these CMP-related problems adversely affect yield and product reliability. To counter CMP-dishing effects, engineers usually add dummy fill to even out layers.

Dave Reed, Blaze DFM's vice president of marketing, says that engineers have traditionally relied on DRC (design-rule-correction) scripts to determine the best places to insert dummy fill. Reed notes that, with every new process, the amount of rules for CMP grows exponentially and the rules are typically too generalized, applying the same amount of fill if it fits a general situation. "Rules-based [fill] is what everybody has been using, but model-based is where everything is heading," says Reed. "We've been working closely with the foundries on their CMP models. The models are much easier to maintain and enhance than these rules-based scripts, and we're not even sure if people will be able to go even one more generation with these DRC scripts. Even today, they can't get an optimal result with just CMP scripts."

Working at 65-nm processes, companies are also now adding polysilicon fill to polysilicon layers to make the shapes look more regular for lithography tools, further complicating scripting. To help designers, Blaze DFM has essentially come up with an intelligent, dummy-fill-synthesis tool. Andrew Kahng, PhD, the company's co-founder and chairman and his team at the University of California—San Diego have found a way to formulate the fill problem, so that solvers can solve it.

 The Blaze IF tool reads CMP models from foundries and scripts from DRC tools. Third-party timing- and power-analysis tools provide data to the tool, and it inserts dummy fill into design layouts to ensure density uniformity and thickness. "We think it will be used at the end of place and route," says Reed. "Anybody who knows timing, which will be the physical-design folks, should take responsibility for this now. Previously, this step took place during DRC. We don't think the physical-design guys should be responsible for your timing." Reed says users feed the tool SPEF (standard-parasitic-exchange-format), SDC (Synopsys-design-constraint), Verilog and VCD (Verilog-change-dump) files, along with a postplace-and-route database of LEF (library-exchange-format), DEF (data-exchange-format), GDSII (Graphic Design System II), and OA (Open Access) database files.

Cypress Semiconductor was one of the tool's beta testers. On a project in 90-nm silicon, Cypress maintained ILD (interlayer-dielectric)-thickness variation that was 56% less than the company achieved with its own advanced-fill method. Reed says that figure is especially impressive given that Cypress' fill method afforded the company only a 2% ILD improvement over using no fill at all. Blaze DFM licenses the Blaze IF for a $250,000 annual subscription.

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