Mentor pumps up ICE-logic emulation

By Michael Santarini, Senior Editor -- 4/16/2007

Mentor Graphics has announced its fifth-generation family of logic emulators, Veloce, which features a new architecture that boasts simulation acceleration and ICE (in-circuit emulation) performance as fast as 1.5 MHz and features a top capacity of 128 million ASIC gates. Mentor Graphics has been in the emulation business for more than a decade and, during that time, the company has fielded several emulation systems, building some and gaining some from acquisitions of Meta Systems, which offered Celaro, and Ikos, which offered VStation.

The new Veloce, says Eric Selosse, vice president and general manager of Mentor’s Emulation Division, is the amalgamation of the best of all those technologies. It features the company’s emulation-on-chip technology and builds on the virtual-wires technology that Ikos introduced half a decade ago to speed performance of its Vstation emulation systems.

Emulation systems typically comprise either a bunch of linked FPGAs or custom programmable ASICs. Traditionally, FPGA-based systems have been easier for EDA companies to design but didn’t offer the performance of custom programmable-ASIC-based systems, such as the one Meta Systems offered in its Celaro emulators. But, in the 1990s, Ikos devised an algorithm to streamline the interconnect and thus the communication of the various FPGAs in the VStation. “You can look at Veloce as a hybrid between what we had in VStation and what we had in Celaro,” says Sanjay Sawant, director of marketing for Mentor’s Emulation Division. With Veloce, Mentor has incorporated the Ikos virtual-wires technology, but, instead of interconnecting off-the-shelf FPGAs, Mentor uses it to speed the interconnect within and between the custom emulation-on-chip programmable SOCs (systems on chips) Mentor designed for the system. The result is a high-performance emulation system to help designers debug and verify large designs.

“From the VStation family, we have the fast runtime, the ability to handle both synchronous- and asynchronous-design styles, a model footprint, and transaction-based acceleration,” says Sawant. “From the Celaro family, we gain the full custom acceleration, fast compilation, and fast debugging.” Each emulation-on-chip SOC in Veloce can hold 500,000 gates of equivalent, reconfigurable macro elements. Mentor implemented the SOCs in a 90-nm, eight-layer copper process.

As for ease of use, the state of the art in logic emulation is for vendors to offer emulation with identical GUIs (graphical user interfaces) and debugging capabilities to those of their simulators and to offer multimode operation. Veloce systems have the same user interface as Mentor’s Questa/ModelSim simulation environments and can handle transaction-based simulation/emulation. Whereas the VStation took roughly four hours to complete a full compilation—that is, to program ASIC logic into the emulator—Veloce does a full compilation in half the time and runs as many as 15 million gates per hour. Mentor also improved the system so that, if users want to add triggers to their designs running on the emulator after initial compilation, they can do so without recompiling the design. Whereas VStation users could do one debugging cycle in eight hours, they can now do three in eight hours. As a result, designers can more quickly program their designs into the emulation system, do emulation runs, debug, recompile, and complete large designs.

Mentor offers Veloce in three configurations. The desktop-sized Solo for both simulation acceleration and ICE accommodates one user and has a 16 million-gate capacity. The reck-mountable Trio 24/48 for simulation acceleration accommodates as many as three users and can handle either 8 million or 16 million gates. The server-sized Quattro simulation-acceleration and ICE system accommodates as many 4 users and has a capacity of 128 million gates. Mentor offers Veloce for sale outright or for rental with prices starting at $24,000.

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