Panelists discuss challenges of interoperable pcell effort
By Michael Santarini, Senior Editor -- 5/3/2007
Several of Cadence’s competitors in the full custom digital and analog tool space are uniting to come up with an open pcell library (and subsequently open pcell language) that will seemingly compete but also interoperate with Cadence’s proprietary SKILL language based pcell libraries. However, the effort called IPL (Interoperable pcell library) is just getting under way and still has technical and perhaps more significant political challenges to overcome.
That’s the main takeaway, from a panel held April 26 at Synopsys Spring Interoperability forum.
Cadence was fundamental in getting the Si2’s Open Access effort under way and developing it. Open Access is a common database that allows different vendors and users to connect their tools together and ensure those tools will operate correctly together in tool flows. But while Cadence has been putting many engineering years into ensuring that Open Access is successful in the standard cell tool flow, the company has publicly refused to facilitate interoperability of the full custom digital and analog flows by not giving Open Access and its tool competitors access to SKILL for pcell development. Cadence has enjoyed a huge market share in the full custom digital and analog layout space for decades, largely because it controls SKILL for pcell development. Pcells are the fundamental building blocks for custom digital and analog circuits much in the same way standard cells are the building blocks for logic based ASIC design. Because Cadence has dominant market share, when foundries develop libraries for their new processes’ process design kits they typically develop SKILL-based pcells first, then sometime later develop libraries for each of the small vendor’s flows. This results in a lot of extra work for the foundries and inadvertently perpetuates Cadence’s dominance in analog and full custom digital. “You can use Open Access to transfer digital design files between tools but when you get to anything analog and you try to open it up, not all of the layout shows up,” said Ed Lechner, director of analog and mixed signal product marketing, Synopsys. “That’s because you have to have Cadence to open up these pcells.”
“I think it is a fair leap of faith to assume that Open Access isn’t going to provide anything but ‘intra-operability’ unless we are going to open up pcells,” said Richard Morse, director of marketing at Silicon Canvas.
Anthony Nicoli, director of marketing for Mentor’s Calibre group, described how in Open Access today, vendor tools hooked up to Open Access can share, read or write most of the essential digital design data in a tool flow, but non-Cadence tools can’t easily read the analog and full custom parts of a design if users don’t have a Cadence flow. Given that most SOCs contain some amount of analog, that’s a problem.
“As an interoperable tool provider we need a complete data set to do advanced dataset analysis with the full context of the design,” said Nicoli. “Things like recommended rule analysis and critical area analysis need to have divices in place so you can understand what’s going to happen in the different layers. Today, yes, you can make those things work but you can’t make them work in a nice, smooth, interoperable flow.”
Michael Ma, vice president of business development at Ciranova, also pointed out that the key word in electronic design automation is “automation,” which is something that analog and full custom tool flows have lacked.
Some would argue that analog and full custom digital by their nature are art forms and that analog engineers are traditionally reluctant to try any new tools that would claim to bring “automation” to tasks that require artistic finesse. But National’s Lin said that simply having interoperability and the freedom to try other tools and not be reliant on simply one vendor would do wonders for analog and full custom design efficiency. He also pointed out that users would be willing to try newer tools if the tools could all read one format and read legacy data. Realistically too during tool license negotiations, having viable competitors in the tool space, would give tool acquisition groups more leverage during contract negotiations.
As a result of all this, several vendors most of who were represented on the panel have united to back Python, an open and more progressive alternative language to pcell development. Then last month, the IPL group fielded its first open library—a proof of concept library—that demonstrates how several different tools from disparate vendors can read a single format and interoperate. With Ciranova tools hooked up to Open Access, other tools can now read Cadence SKILL based pcells.
Lin said that “the IPL effort is one big step in the right direction,” but to reach its full potential, the industry has to converge on a set of standards for Pycell development to ensure that disparate tools can all read a single Pycell library. “There is no reason an analog design world can’t adopt a methodology much like digital,” said Lechner. “In the digital world anybody can download an artisan library for free, run it on any Verilog simulator, any place and route tool and any verification tool. There is no reason that you can’t do that today because all the infrastructure is in place. All it takes is a group of people in actually furthering the cause of analog productivity to get involved in the IPL initiative.”
Indeed, the other panelists, all members of IPL, noted that their respective tools can indeed all read the current proof of concept library that the IPL group has now made freely available on its website, but conceded the library and the scope of how cells are described with the language still needs refinement. “The next step is to create a set of standards, just like Verilog or GDSII standards,” said Lin. “With these standards plus IPL, I think we can accomplish our mission.”
Lechner noted, however, that this isn’t the first effort to come up with interoperable pcells. A few years back, many of these same members tried to get the industry to back a single standard process design kit. The effort fizzled out under Accellera and Lechner said it is largely because the effort was trying to do too much at once. Thus the IPL is staying more focused on pcell development.
“Probably 70 percent of PDKs is trying to get the pcells right, and then the other 30 percent is all the other pieces,” said AWR CEO Dane Collins. “So if we can figure out how to pool our resources and develop one methodology for developing pcells, there really won’t be any more work on our parts—we’ll be able to share the work we do. Not necessarily work harder but work smarter.”
Audience members asked if learning the Python language would be too difficult for engineers and foundries used to describing pcells with SKILL. George Janac, CEO of Silicon Navigator, who worked for Cadence for many years after Cadence acquired his earlier start-up High Level Design, said that Python is indeed very similar to SKILL, but is actually a more elegant and easier to use development language for pcell description.
Creating successful standards, meanwhile, isn’t simply a matter of ensuring there is a nice, new, easy-to-use format. Most standards, especially in EDA, run into political issues and are driven by user demand.
Panelists agreed that the effort is unique in that it could conceivably run into opposition from certain big users, as well as from Cadence. Some of the wealthiest and largest semiconductor vendors in the world have purchased from Cadence the right to use SKILL for pcell development (something which Cadence doesn’t offer tool competitors). This seemingly has allowed these large vendors to gain a competitive advantage, as it allows them to develop their own tools and ensure tighter more efficient flows and get a jump on the competition because foundries traditionally develop SKILL-based PDKs before they develop PDKs with alternative pcell languages.
Those involved in the IPL effort are well aware of the many types of pitfalls of standards efforts.
Ma notes that the IPL effort is open to any and all comers, but said they must have the right motivation to make IPL a reality.
Cadence was invited and decline to participate in the panel.
© 2009, Reed Business Information, a division of Reed Elsevier Inc. All Rights Reserved.