IBM Inside, part two
By Ed Sperling, Editor in Chief -- 6/19/2007
Tom Reeves VP of semiconductor and technology services at IBM, sat down with Electronic News/Electronic Business to talk about the future of chip development, competition and why CMOS has a very long future. What follows are excerpts of that conversation.
Q: With complexity escalating at each new process node, can the tools to develop hardware keep up?
Reeves: Until folks try 100 designs or so, we won’t know the ultimate answer. It’s certainly getting more difficult, and we at IBM certainly think the investments we make in statistical timing, power management, noise awareness and noise avoidance, continue to show increased benefits in these highly complex design environments. We’re seeing recognition of that from our supplier base. I see the trend toward an increased reliance on very high-tech, leading edge tools and an integrated stack.
Q: But who’s going to provide those tools, IBM or its partners?
Reeves: Today, for the high-end digital designs, most folks would recognize IBM is providing that design infrastructure. I saw one analyst report recently that said that’s 70 percent of the high-end digital design projects on a worldwide basis. Certainly the three gaming platforms are on that list. We’re working closely with AMD to help them with their design challenges in addition to our classic ASIC clients.
Q: Are you developing what are considered classic EDA tools, though?
Reeves: IBM has 25 years of history and continues to invest in proprietary EDA tools. The largest single category is timing. We moved from static timing tools, first in the industry, to silicon variation-aware timing, the soonest in the industry, and today we are still the only company offering a full statistical timing approach or sign-off. It’s paying very good dividends in terms of results. In addition, we have secondary tools that I’d put in the category of noise awareness and noise avoidance, power management, place and route, and test generation.
Reeves: We’ve made all these tools available as part of our ASIC offering. Clients doing IBM ASICs have access to all of these tools as part of that flow. Selectively, we will do design consulting or turnkey design service work using all of the tools, which is true of all three gaming processors and many other projects including design consulting on AMD’s x86. But we do not have any intention of becoming a merchant tool vendor. We offer a much higher level of total value when we offer it as part of an integrated design flow—including product management, hardware engineering and the best base silicon available.
Q: You view your tools as a competitive advantage, then?
Reeves: We stand alone in the worldwide marketplace in that we are not just a foundry, not just a design tool company, not just a fabless silicon design company and not just a system company. We do all four of those things, and we’re the only company on the worldwide landscape that is that integrated from silicon process development, EDA tools, chip design, card design and system design.
Q: So how would you describe IBM?
Reeves: The $90 billion-plus IBM is rich in data processing, software, and services. The technology side of IBM is a micro-version of that statement. We, more and more, are not just a hardware company. We are rich in software, EDA design flow, and we’re growing our design services business.
Q: So given that, who are your competitors? Is it Intel, EDA vendors, or all of the above and more?
Reeves: There are a lot of formidable competitors on a worldwide landscape, whether it’s microprocessor solution providers. In the gaming segment we’ve won that battle. In the ASIC market, we’ve predominantly won that battle. In mixed signal market we’re well on our way to winning that battle, both in terms of migrating gallium arsenide into silicon germanium, having the best silicon germanium design flow and tools and technology.
Q: So IBM also offers a full spectrum, all the way to complete chips?
Reeves: At the very low end of the spectrum, we have leadership hardware with the best hardware-to-electrical models. By having high accuracy in the electrical-to-physical models, even companies doing an entire analog design flow on their own with their own choice of tools get a far more predictable result using IBM’s hardware-to-electrical models than what is available from other foundries. Then you can move above that model to where we provide all the libraries and the intellectual property and an integrated design flow that works on our technology and those of our partners, or our ASIC design flow that works on our technology and our partners’ platforms. At the very top of the stack you can define nothing more than what you want the chip to do and we’ll do the rest.
Q: Where are you seeing the most activity these days?
Reeves: We went from data processing to networking, both wired and wireless, then took complete control of the gaming console, and now we are expanding in consumer electronics and the cellular handset. There are cases where you’ll find five IBM chips in a single cell phone. We shipped 1 billion chips last year, and that was driven by participation in the cell phone market.
Q: What do you see as the next big growth market?
Reeves: Wireless, whether that’s traditional cell phones, or an integrated MP3, cell phone, video appliance. But wireless connectivity will be the future.
Q: Let’s drill down a little bit into the handset market. Where exactly does IBM play in these devices?
Reeves: There’s digital baseband. That exists in our foundry access point and our ASIC access point. There’s an eDRAM (embedded DRAM) ASIC in a Sharp cell phone that’s available through Vodafone. In analog baseband, most of our participation is in CDMA. We’re also in GPS for navigation, TV tuners, which are very big in Japan and Korea even though there is no network available in the United States yet. In Japan, 100 percent of the company is enabled for over-air TV broadcast, and partners like Microtune would be a typical collaborative partner for us. In power amplifiers, we’ve added another technology that enables the migration from gallium arsenide to silicon germanium.
Q: Will multicore put all that in one chip or will it still be five chips?
Reeves: When you look at what’s going on in the handset, you had many different technology types from gallium arsenide through old lithography level BiCMOS or mixed signal. Perhaps there was the start of silicon germanium. There is advanced digital baseband technology with very leading-edge lithography. It was a collection of technologies. We have been leading a migration path. The gallium arsenide leads to silicon germanium, so the TV tuner function, the GPS function, the power amp function, and some other unannounced functions all can be implemented in silicon germanium. That includes 802.11 radio for a wireless Internet access point. Then, on the baseband side, as things move to RF CMOS rather than the historical bipolar or BiCMOS, the integration of the baseband with the analog baseband becomes a reality. You can get to a single-chip cell phone with low-end design points. So I see a dramatic reduction of total part count. I don’t see eight functions on one chip. But you’re definitely going to go from eight disjointed technologies to two or three very central technologies that allow a lot of integration.
Q: Is that harder or simpler to design and manufacture?
Reeves: It’s more challenging if you’re trying to do the equivalent of three chips on one die. By definition, it’s a harder task. A single point error will impact all three functions. But it’s a lower cost and lower power solution, and typically higher performance.
Q: Are you making these chips, or is that being done by your partners?
Reeves: Today, all of the silicon germanium is manufactured inside IBM. The bulk CMOS and silicon on insulator we manufacture outside of IBM through our platform partners as well as inside IBM.
Q: How prevalent is silicon on insulator?
Reeves: We started using it at 0.18 [microns] for processors. We used it through the 0.13 generation, at 90nm expanded it to the x86 processor through AMD, and expanded it to all three gaming platforms at 90nm. That continues at 65nm. Several of the gaming platforms are in production at 65nm. We are expanding SoI from the x86, IBM Power and gaming segments broadly into the networking industry where there will be hundreds of chips designed. The whole world of switch fabrics, network processors, ASICs on line cards—the entire Internet at 45nm will be on silicon on insulator.
Q: Is the ASIC still the same ASIC we’ve always known, or is it merging with ASSPs, as some executives contend?
Reeves: I haven’t seen them merge. The major network equipment providers continue to do classic ASIC engagements, in the non-trivial part-number count, with logic front end design and verification by the network equipment provider, and physical design and automatic test generation and full package qualification product engineering by IBM. What we do see is a growing list of ASSP providers, while that’s a fairly short list in the networking market, are implementing their ASSPs as IBM ASICs. They’re using the same design infrastructure that Nortel or Cisco use, but they’re designing the network processor and trying to sell it to more than one company.
Q: IBM has made a lot of noise about developing ecosystems, but it appears from what you’re saying that much of IBM’s work still is playing the role of general contractor. Is that correct?
Reeves: It’s a hybrid model. Our basic CMOS/RF CMOS silicon technologies are co-developed and co-manufactured and offer assurances of worldwide supplies that are unmatched. We work with those partners to have a common design platform for clients to use. We then supplement that with the IBM general contractor/add some unique timing, wiring, noise management, product engineering services.
Q: Where does the money come from? Is it contracting services or the technology you’re selling or co-developing?
Reeves: It’s a mixture. Having the kind of leading-edge semiconductor processes, like silicon germanium, 45nm low power and 45nm SoI—the competitive health of those technologies is part of the answer. The second part of the answer is the design infrastructure, the product engineering, the know-how to design and use that IBM brings to the market.
Q: Is the market different for your technology from one continent to the next?
Reeves: I don’t see much difference in the geographic marketplace. A network equipment provider in China—Huawei—is doing the same kind of ASIC design as a European or North American network provider. The consumer electronics providers are using a different technology—a low-power optimized technology—but using similar design flows.
Q: Is there really any differentiation from one vendor to the next, then?
Reeves: The common platform is differentiated in that it’s a multi-source available common technology. That differentiates it from single-company technologies. We’re growing that on CMOS and RF CMOS, and we see an increasing number of partners growing it on silicon on insulator.
Q: What changes at future generations, and can everyone continue to play at the next process nodes?
Reeves: We are not just shrinking lithography and buying the next-best stepper. Everything in the last five years has included changes in basic materials and process engineering, whether it’s strain engineering, embedded silicon germanium in our SoI, our Airgap technology, our high-k metal gate—these are fundamental R&D, not just shrinking. It’s going to be very hard for many, if any, independent companies to continue in that race.
Q: I would think it will be hard for companies to continue at future process nodes, particularly at 32nm and 22nm without government research dollars, not just corporate investment.
Reeves: That’s true. The U.S. has taken some historical steps with Sematech, and the Albany Nanotech Center is a very positive step in that direction.
Q: Will IBM expand its ecosystem to adjust to this?
Reeves: Yes. More and more, I see us moving from a process-development only partnership and co-manufacturing to an IP design flow partnership expansion. Some of the newer participants have those business models.
Q: But because of the increasing integration required, will the ecosystem also include OEMs and subsystem manufacturers?
Reeves: It’s certainly getting more complicated. We’ve moved from processor-centric agendas to low-power consumer agendas. There are low-cost agendas.
Q: At what point do you involve the cell phone maker, for example?
Reeves: Typically, an ASSP provider needs to reach in that direction to have integrated software stacks. IBM has positioned itself as a collaborative design partner, where we’re providing enabling hardware technology. That does not enable us to go into software stacks and end solutions. We’re doing that from a different angle. Part of our global engineering solutions is software-oriented. We’re working on joint software development centers in Europe and in Asia. The automotive and the airline industry are ripe for the movement toward a system-level solution, much like you would do for a server, at the automobile or airplane level. Rather than having a series of discrete isolated systems—brakes, navigation, entertainment, lighting—there can be integrated systems. That is an area that IBM, given its broad agenda, can bring engineering solutions. We’re not coming at it from a chip perspective, though.
Q: Do you foresee the alternative energy market as an opportunity, as well?
Reeves: We’re looking at how the Cell processor can improve the efficiencies of energy distribution and management. We also have some unique software capabilities we use for critical resource semiconductor lines that have been adopted by most semiconductor companies worldwide. They manage very complex supply chain flows of wafers, tested wafers, modules, bills of material, even up to software. Those tools can be directly applied to the energy industry in terms of how your regulate sources and uses of energy on power grids.
Q: What is the next hot market for IBM? Is it refinements of what’s there, or is it a new direction?
Reeves: I certainly see continued expansion in wireless technologies. GPS will be on handsets, and TV tuning will come to the United States. It’s just a matter of time. Both of those are major changes in what we carry around and what that enables.
Q: Let’s swap topics. IBM has developed charts that show CMOS running out of steam the way bipolar technology did. Are we witnessing the end of CMOS?
Reeves: High-k metal gates represent a game-changing event. When you look at the increasing power of CMOS—and the analogy that’s drawn is whether this is repeating where bipolar led us—a typical chip at 65nm and 45nm is half standby power and half active power. High-k metal gate reduces that standby power by 100x. High-k metal gate is a game changer in that projection of where CMOS is going in terms of power. Now that only addresses half the equation—leakage of standby power. It doesn’t address active power.
Q: How do you improve the active power?
Reeves: Increased performance, which you can achieve with silicon on insulator, allows you to achieve lower voltage for a given performance level. Silicon on insulator actually becomes a low-power solution, unless you’re using it for a high-performance solution.
For part one of this special report, click here.
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