Leakage grows, high-k approaches: The world of 45-nm CMOS

By Ron Wilson, Executive Editor -- 7/17/2007

Even as many design teams are contemplating the move from 130-nm to 90-nm technology, at the Semicon West conference in San Francisco this week the world begins at 45 nm. Equipment and materials vendors are tooling-up the industry for the launch of the first production 45-nm processes in the near future. Matsushita has already announced production of some sort of 45-nm process, while Intel, AMD, Texas Instruments, and the Common Platform are expected to start 45-nm production beginning either in the second half of this year or next year.

While much of the public attention regarding 45-nm technology may fall on lithography, the big questions on the minds of cell designers and chip designers are leakage current, SRAM, and process variations. "We have to deal with higher leakage current in our cell designs," said ARM fellow Rob Aitken. "Not only is the leakage current higher, but a larger portion of the leakage current is gate leakage, which doesn't drop off with decreasing temperature as rapidly as substrate leakage. In that way it's a new issue."

"Particularly at low voltages, chip designers are going to have to talk with their memory vendors. They may need to employ techniques like read- and write-assist in order to find a design that will yield." —Rob Aitken, ARM

Aitken said that even though cell designers are doing their best to cope with the increased leakage, it will still be up to chip designers to deal with the problem at the block level. "We can put the cells in the library to support techniques for managing leakage current, but in the end it's up to the chip designers," he said.

A related problem has been the design of SRAM cells. Bit-cell design is a compromise between stability and writeability. At 45 nm, an acceptable compromise between the two criteria proves elusive. If the cell is stable enough to retain data, it's very hard to write. Foundry engineers have primarily been the ones tasked with addressing this problem; they've done the yeoman work in creating stable yet usable bit cells. Still, memories at 45 nm won't look exactly like those at larger geometries.

"We can hide a lot of these issues in the memory array," Aitken said, "by doing things like reducing the number of rows in a bank. But particularly at low voltages—say, V_DD –20%—chip designers are going to have to talk with their memory vendors. They may need to employ techniques like read- and write-assist in order to find a design that will yield." Aitken emphasized that it's usually possible to get an array that meets given performance criteria, but at the cost of some combination of area and power.

Increased variations will also be a fact of life at 45 nm, Aitken said. Cell designers will shoulder much of this burden, by complying with increasingly restrictive design rules and in some cases substantially changing traditional cell designs. But some of the burden will fall on chip designers as well.

For example, Aitken pointed out that most 45-nm processes require unidirectional poly at fixed pitches. "In some cases, if you comply with this requirement you can see 10% better performance," he said. But using only one orientation for poly lines makes the traditional layout of flipflop cells, for example, impossible. ARM had to find an entirely new layout to comply with the rules.

Another example of substantial changes in internal cell routing is the SRAM bit cell. But in this case, the change will show through to the user. "Requiring the same orientation for logic and memory cells means the power routing interacts differently with the layout than in conventional memory arrays," Aitken warned.

Despite containment efforts, chip designers will have to deal with higher variability in electrical parameters. Variations will occur between wafers, between dice, and even across a die. Also, variations with age are becoming an issue. One such variation that is going to be significant, although not a showstopper, is NBTI (negative-bias temperature instability). This effect gradually degrades the performance of P-FETs over time. Aitken said that some designers are looking at "canary circuits" designed to operate right on the timing margin of a die under worst-case conditions and to give early warning if NBTI is about to compromise the function of the chip.

Battling leakage

Many of these issues come down to simple matters of physics. But leakage current is one area where process engineers and equipment suppliers are fighting back. Today Applied Materials announced a complete technology for fabricating MOS gate stacks using a Hafnium-based high-k dielectric and metal gate materials. The result of the combination is to offer MOS transistors that closely resemble earlier generations of MOS devices in operating characteristics, but with substantially less gate leakage for a given threshold voltage.

"We think of it as permitting scaling to continue for planar MOS transistors to 45 and 32 nm," said Gary Miner, CTO of Applied's front-end products group. Reportedly Intel has adopted the Applied gate stack technology for its initial 45-nm production, and both TI and IBM have announced that they will phase in new materials during the 45-nm generation. Significantly, the members of the Common Platform (IBM, Chartered, and Samsung) have not indicated that they will use high-k at 45 nm, so the technology may not be available in a foundry process until 32 nm.

Miner and Applied fellow Reza Arghavani explained that the new gate stack is far more than just substituting a new dielectric for conventional silicon oxynitride. Finding a Hafnium oxide that would work required considerable research. During that time, it became apparent that if the material came in contact with the transistor channel's silicon lattice, an effect called soft phonon scattering would come into play. This scattering, caused by the influence of the electric dipoles of the Hafnium atoms' asymmetric D-orbitals on the normally symmetric lattice of silicon outer electron shells, would substantially reduce carrier mobility, taking away most of what has been gained by stress engineering.

So the gate stack starts out with an extremely smooth, 6- to 8-Angstrom layer of silicon oxynitride over the channel. This layer is there primarily to keep the high-k material far enough away from the silicon lattice to reduce soft-phonon scattering. This is followed by a thin layer of high-k Hafnium oxide. Then comes the metal gate.

The metal gate is itself a stack. The process requires two different metals with two different work functions, one for P and one for N transistors. If the work functions don't match closely to the work functions of P- and N-Poly, the transistor threshold voltages will not look like those of conventional transistors, and circuit designs will have to change substantially. A thin layer of the proper metal goes over the high-k dielectric film. Then the rest of the gate well is filled with aluminum or tungsten.

Several ways of fabricating this stack exist, but most of them require a very precise, very small gate opening. "These demands went well beyond evolutionary development in etching technology," said Applied global product manager for etch products Dimitris Lymberopolous. The company developed a high-temperature etch process that successfully dealt with nonvolatile etch byproducts and with proper shaping of the critical bottom of the gate well, allowing not only better yield but precise critical-dimension control over gate length.

Together, the new gate stack and new etch technology promise to give device designers a threshold-versus-leakage tradeoff they haven't enjoyed for several nodes. Transistor designers can turn this knob to give themselves either faster transistors or lower gate leakage. But there are costs.

Process engineers face three new materials that must be integrated into the process. Physical designers, mask makers, and fab operators must deal with on the order of 15 new mask layers. And cell and chip designers must contend with more sources of variation in electrical parameters. One of these will be PBTI (positive-bias temperature instability), a new effect for N-FETs to match the problem of NBTI.

It seems likely that only those in search of the highest performance levels will take on the challenges of high-k/metal-gate technology at 45 nm. But by 32 nm, oxide scaling becomes so critical that not only gate leakage but also gate integrity and gate uniformity may force the use of the new gate stack. At that point, the ground broken by Intel, AMD and IBM may become much more widely trodden.
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