EDA startup Pyxis unveils yield-driven IC router NexusRoute

By Michael Santarini, Senior Editor -- 9/25/2007

Startup Pyxis Technology this week is formally introducing the commercial place-and-route system it promised more than two years ago. Given Mentor Graphics' acquisition of Sierra Design earlier this year, IC design groups now have more choices than ever when it comes to shopping for IC place-and-route tools. However, as the selection is larger, the choice may be a bit more difficult.

Since Pyxis announced its existence and its intent to enter the place-and-route market, the company hired a new CEO and more staff, raised more funding, and diligently beta-tested and primed its product for commercial use.

This week the company will finally make its place-and-route offering, called NexusRoute, available to the general market. The company is also announcing NexusYield design services to help its customers route blocks and chips.

NexusRoute is a hybrid gridded and shape-based router that is tightly coupled to foundry data, according to Pyxis, which officially calls it an "automatic, yield-driven router."

It's certainly no secret that starting at the 65-nm process node, implementation tools have had to become savvy of manufacturing issues. Indeed, in preparation for 45 nm, the big four EDA companies have been adding DFM (design for manufacturability) tools to their tool lineups and are in the process of integrating DFM awareness into their place-and-route flows. Pyxis thinks its new offering will give users an edge over the competition in that the new router was built from the ground up to incorporate manufacturing data into the routing process.

"What we are trying to address are yield and manufacturability issues," says Phil Bishop, Pyxis's CEO. "There are three major components of yield: random defects affecting random yield, printability issues affecting systematic yield, copper dishing [CMP] affecting parametric yield. More and more we're seeing yield become design-dependent. A lot of work has gone into manufacturing equipment and fab optimization. And where we see room for improvement is on the design side. For Pyxis in particular, we are seeing discontinuities at 65 nm, especially in lithography. These discontinuities are what we are trying to address with our routing technology."

Because most vendors are adding DFM technologies to existing place-and-route systems, Bishop says, the flow they typically endorse is iterative. Users perform placement and routing, run timing and signal-integrity analysis, perform a post-route optimization, then run DFM analysis (yield, lithography, and CMP, typically), and then finally run physical verification. This flow typically requires users to run multiple iterations between the various tools before they complete a design, which costs time and money. After they complete the chip design, the designers have to send it to the fab, which may discover further problems, which will require changes back in the design step or even new mask sets, which are extremely expensive.

NexusRoute will consolidate routing, timing analysis, signal-integrity analysis, post-route optimization, and DFM (yield, lithography, and CMP) analysis into essentially a single-pass flow, says Bishop, who claims it will reduce the design and manufacturing cycle 4×.

"What we are doing is focusing on a comprehensive single-pass solution and are zeroed in on a new approach where we link manufacturing with design tightly together to achieve manufacturing closure," Bishop says. "Within the database and the tool, we are looking at the routability, the throughput of the core-based routing, timing closure, and signal integrity. And additionally, and concurrently, we are also looking at manufacturing effects. Things like spreading wires, fattening wires, protecting vias with secondary shapes or redundant vias—all of these are attempts at trying to remove yield detractors that are part of design-based yield. It's intended to a be a single-pass solution so you do this all along then you have a single-pass output that is optimized in all three domains."

The environment allows users to instantly see, as they route, what effects their design will encounter in the random-, systematic-, and parametric-yield domains, Bishop says. Pyxis integrated 34 DFM rules into the router to drive functions like wire widening and spreading, jog elimination, 3D wire balancing, metal and via fill, lithography pattern elimination (necking and bridging), and via minimization and via protection (double cut and extra shapes).

Many of the data for the rules running on the Pyxis tool come from Pyxis' DFM-analysis partners PDF Solutions (which provided data on random and systematic yield) and from Brion-ASML (which provided data on photolithography analysis). "We also worked closely with Ponte to use their software for analyzing random yield effects," Bishop says. "In all these cases we are trying to find yield issues we can eliminate with the technology, or in Brion's case, finding necking and bridging issues and eliminating them."

NexusRoute actually reads PDF Solutions' PDFx models, which are yield-ramp fail-rate data models. "It is actually built in to our technology so there is an opportunity to do this analysis on the fly," Bishop says. "It's a big part of what we are doing. We're not just saying we're improving yield, we're measuring it and trying to then give customers feedback on exactly what the router has done to incrementally improve the yield of the design."

The PDFx data is especially effective in the router if the foundry the customer is targeting happens to be one of the fabs for which PDF Solutions has done characterization services. If customers are targeting a foundry process PDF has not characterized, they can use generalized PDFx models of a given process node. "We can also read in any fail-rate data provided by the foundries," Bishop says. The tool also reads the standard physical-design formats such as LEF, DEF, .lib/Liberty, and SPEF to interface with other vendors' flows. The company is also a member of OpenAccess for interoperability with third-party flows and counts Silicon Canvas, the provider of the Laker analog and full-custom layout tool, as one of its partners.

At its core, NexusRoute includes a global router and a detailed router that Bishop says are closely coupled. "Traditionally what you see is that people will do a global and then [a] detailed [route], and then iterate all around several times," Bishop says. "That's very time-consuming and expensive. Our routers are joined at the hip. The detailed router will not escape from the tunnel given to it by the global router unless the designer absolutely lets it. We do most of our optimizations at the global-route stage, and the global router is about 10× faster than the detailed router, so you can make a lot of runs to try things out with the global router and then have a high probability of only needing to do one pass through with the detailed router."

NexusRoute is primarily a gridded router, but is shape-aware, Bishop says. "Being shape-aware is pretty important for routing below 65 nm because you are doing DRC [design-rule checking] while you are routing, and you have to be really high-fidelity," he says. "Because of that we are very fast, and if I turned all the DFM functions off, we'd be very competitive with the fastest routers out there. NexusRoute is very fast router, but if I turn on all the DFM features, it depends on what I'm trying to ask it to do. It will slow it down some, but at the same time, I don't have to do post-route fix ups."

The tool is also multithreaded and supports distributed processing to speed up runtimes, which is especially useful during detailed routing, when the compute-intensive shape-based features come into play. "What we lose in performance by activating the DFM features, we can make up with multithreading and distributed processing," Bishop says.

The company claims that in benchmarks against the major competitors in the IC-routing space, NexusRoute achieved between a 5.1% and 11.1% percent yield improvement on 90-nm designs and between 6.8% and 7.5% yield improvements on 65-nm designs (both cases testing just random and systematic yield). The company has not yet benchmarked on 45-nm designs.

Pyxis has been qualified by AMD and has endorsements from Chartered Semiconductor Manufacturing and Microsoft's Xbox design group. The company claims to have routed and taped-out several blocks and chips for companies, but no customers to date have produced silicon using the tool.

Pyxis is offering NexusRoute for $400,000 for a single-year subscription.

Because Pyxis is the newest player in a tool space that is very hotly contested by all of the big EDA players, the company is also trying out a unique services model, in which it is offering customers routing, flow-assessment, and library-assessment services.

Specifically, Pyxis is offering NexusYield Service, in which the company will route blocks or chips for companies with its tool for a fixed fee of $50,000 per month. The hope seems to be that early customers will be so impressed with the results that they'll decide to buy their own licenses. The next offering is called NexusDFM Service, in which the company will perform a DFM design-rule and flow assessment for $50,000 per month. The last is a NexusLib service, in which the company is doing routability and DFM-quality library assessment for $50,000 per month.

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