IMEC, Powerchip expand sub-32-nm CMOS research
By Ann Steffora Mutschler, Senior Editor -- 1/29/2008
To perform R&D for sub-32-nm memory process generations, Leuven, Belgium-based nanoelectronics research center IMEC and Hsinchu, Taiwan-based flash memory and DRAM provider Powerchip Semiconductor Corp (PSC) said today they will work together within IMEC's advanced lithography program addressing immersion, double patterning and EUV lithography challenges.
From March 2008 onwards, PSC researchers will reside at IMEC to closely collaborate with IMEC's researchers in the abovementioned areas to build fundamental understanding and develop technologies for the 32 nm node memory process generation and beyond.
This agreement adds to IMEC’s memory technology work. Prior to this agreement, IMEC had grouped the top five leading memory suppliers including Micron, Qimonda, Samsung, Elpida and Hynix, to collaborate within its global research platform to scale CMOS beyond the 32nm node.
PSC chairman Dr. Frank Huang noted that as photolithography technology approaches 32nm, physical limitations are encountered while development costs are increasing, driving the need for alliances and joint development in the industry.
Gilbert Declerck, president and CEO of IMEC concluded that, “PSC's joining demonstrates our ambition to further expand our program with new leading partners, on the path to technologies below 32 nm. It emphasizes the increasing strength of our memory partner network, which is unique in the world. It also illustrates our commitment to further enforce our business in Taiwan, at the time when we're opening IMEC Taiwan in the Hsinchu Science Park.”
In other IMEC news, yesterday, the research group said it would collaborate with AMIS on next-generation Smart Power integration technologies.
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