Toshiba touts 43-nm CMOS 16-Gb NAND flash

By Ann Steffora Mutschler, Senior Editor -- 2/7/2008

Tokyo-based Toshiba Corp and its Irvine, Calif.-based subsidiary Toshiba America Electronic Components this week detailed its 16-Gb NAND flash memory chip, manufactured on its 43-nm process technology co-developed with SanDisk Corp, during the International Solid-State Circuits Conference (ISSCC) that was held in San Francisco this week.

Toshiba made clear that when in relation to memory density, Gb means 1,024x1,024x1,024 = 1,073,741,824 bits, and that usable capacity may be less.

The 16-Gb products have a chip area of 120-square millimeters, less than 30% that of same density NAND-flash memories jointly developed by Toshiba and SanDisk and fabricated with 56-nm process technology.

The company noted that memory cells are grouped and controlled in NAND strings of 64 cells aligned in parallel, double the number of 56-nm devices, with a dummy word-line at either end to prevent program disturbance, which is meant to reduce the number of select gates and improve memory area efficiency.

Modification of the peripheral circuit design also contribute to a reduced chip area with the addition of high voltage switches to the circuit that reduces the number of control-gate driver circuits required to drive word lines, and ground buses that are routed on the memory cell arrays.

Toshiba said it will start shipping commercial samples of new 16-Gb single-chip, multi-level cell NAND flash memories today, and plans to start mass production next month.

Further, Toshiba said it intends to start mass production of 32-Gb NAND flash memories in Q3, with the new chips to be manufactured at its Fab 4, the latest 300-mm wafer fabrication facility at Toshiba's Yokkaichi Operations in Mie prefecture, Japan.

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