Synplicity introduces secure IP flow for FPGAs, signs ARM, Tensilica as partners

By Matthew Miller, Editor-in-Chief, EDN.com -- 4/15/2008

At the Embedded Systems Conference today, Synplicity has introduced what it calls the industry's first complete, encrypted design methodology for FPGA implementation. The ReadyIP program, according to the company, allows designers to easily assess and incorporate IP from third-party vendors into their designs using Synplicity's synthesis tools, Synplify Pro or Synplify Premier (shown below).

ARM, CAST, Gaisler Research, Synopsys, and Tensilica have signed on as partners in the ReadyIP initiative.

Key elements of the initiative include: Synplicity's OpenIP encryption and digital-rights-management technology, which the company has donated to the IEEE (Institute for Electrical and Electronics Engineers) for standardization in the IEEE's P1735 Working Group; System Designer, a vendor-agnostic IP-integration technology that, as of today, is part of Synplicity's synthesis products; "push-button" Internet access to third-party IP within Synplicity's FPGA design tool; and support for the SPIRIT Consortium's IP-XACT packaging format, which aims to ease the mixing and matching of IP from disparate sources.

As important as simplifying the integration of third-party IP, according to Synplicity, the ReadyIP initiative will make it easier for organizations to securely share and reuse IP internally.

The initiative will give designers free evaluation access to ARM's Cortex-M1 FPGA processor, and at the show, the companies are demonstrating a Cortex-M1-based application that includes peripheral IP from CAST and was constructed using Synplicity's FPGA-synthesis tool. Tensilica will provide the Diamond Standard 106Micro processor core, which it calls the industry’s smallest licensable 32-bit processor core based on an industry-standard architecture, free of charge through the Ready IP program. At the show, Tensilica and Synplicity are demonstrating the process of downloading the processor through the latter's tool flow.

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