Mentor Graphics acquires NXP design-for-test technology, developers

By Matthew Miller, Editor-in-Chief, EDN.com -- 5/6/2008

Mentor Graphics and NXP Semiconductors today announced an exchange of DFT (design-for-test) technology and talent that will see NXP adopting Mentor's tools while Mentor gains rights to NXP's internal DFT technologies and acquires a group of NXP's DFT developers.

Under the agreement, NXP will begin using Mentor's DFT tools, including its TestKompress compressed-pattern-generation tool and its YieldAssist failure-diagnosis tool. Meanwhile, Mentor will gain access to tools and technologies NXP had developed for its own use. In addition, Mentor's design-for-test product division will absorb an undisclosed number of NXP DFT developers, who will now work in a new R&D facility in Hamburg, Germany.

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"NXP (starting out as Philips Semiconductors) has a very long history of developing internal tools for DFT and manufacturing test," said Greg Aldrich, director of marketing for Mentor's design-for-test product line. "They have been primarily focused in the areas of automatic test pattern generation (ATPG), test data compression, and diagnosis of test failure data for the purposes of failure analysis and yield learning. All of these technologies are very complementary to Mentor's existing product line and product roadmaps."

The development team moving over to Mentor is a "seasoned" one, including some members with more than 20 years of DFT experience, Aldrich said. "Adding such highly qualified engineers to Mentor's DFT development team will allow us to accelerate development and delivery of new products and test technologies," he said.

Furthermore, as NXP transitions from its internal tools to Mentor's DFT products, Mentor will be integrating various technologies from the internal tools into its commercial releases. "I expect some of these technologies will provide value to all Mentor DFT customers," Aldrich added.

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