IMEC improves performance for 32-nm simplified high-k/metal gate process

By Ann Steffora Mutschler, Senior Editor -- 6/18/2008

At the VLSI Symposium being held this week in Honolulu, Hawaii, Leuven, Belgium-based nanotechnology research center IMEC reported that it has improved performance for its planar CMOS semiconductor manufacturing process using hafnium-based high-k dielectrics and tantalum-based metal gates for the 32-nm CMOS node.

Also from the VLSI Symposium: “NEC shows novel thermal monitor for SoCs”

Working in collaboration with its sub-32nm CMOS partners including Intel, Micron, Panasonic, Qimonda, Samsung, TSMC, NXP, Elpida, Hynix, Powerchip, Infineon, TI and ST Microelectronics, IMEC said it advanced the inverter delay from 15ps to 10ps, and also simplified its high-k/metal gate process by decreasing the number of process steps from 15 to 9.

The high-performance (low-Vt) high-k/metal-gate CMOS was reached by applying a thin dielectric cap between the gate dielectric and metal gate structure, and both gate-first and gate-last integration schemes have proven to be successful, IMEC said.

While the gate-last scheme is now being introduced in production for high-performance products, IMEC believes the gate-first option is well-suited for low-cost applications if its complexity can be reduced to the standard CMOS process flow. One of the possibilities for gate-first is a dual-metal dual-dielectric process flow using mostly hard masks to pattern nMOS and pMOS regions selectively.

By applying conventional stress boosters to its gate-first dual-metal dual-dielectric high-k/metal gate CMOS, IMEC noted that performance of nMOS and pMOS transistors increased 16% and 11% respectively, resulting in an inverter delay improvement from 15ps to 10ps – which demonstrated for the first time the compatibility of conventional stress memorization techniques with high-k/metal gate.

Further, IMEC explained that it has simplified the process complexity from dual-metal dual-dielectric to single-metal dual-dielectric by using soft-mask processes and wet removal chemistry, which reduces the complexity by 40% or 6 steps compared to dual-metal dual-dielectric, as well as allowing simpler gate-etch profile control and it offers better prospects for scaling. Also, IMEC proved that the use of La and Dy capping layers do not show any reliability issues.


(Source: IMEC)

SEM and x-TEM of nMOS/pMOS boundary in ring oscillator.

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