Multiarchitecture DSP road map refines power-efficiency-versus-performance balance

By Robert Cravotta, Technical Editor -- 7/22/2008

Texas Instruments’ multiarchitecture-processor plans expand a low-power-design emphasis beyond the fixed-point C550x series of processors and applies it to the high-performance C640x family, the floating-point C674x family and the high-integration OMAP (Open Multimedia Applications Platform)-L1x family of processors. This shift addresses developers increasing requests for processing options in different power budgets rather than power consumption for a given level of performance. New devices in each of these product lines will support software and pin-for-pin compatibility so that developers can support immediate development with current devices and then migrate to devices that consume less power.

The first devices available in this lineup are a new generation of the C674x floating-point DSP family; they will become available for sampling in the fourth quarter of 2008, and prices will start at less than $9 (100). The devices support a deep-sleep-power draw of 6 mW using a 0.95V core with the real-time clock on and the DSP and all peripheral clocks off. The power draw is 12 mW in standby mode with the same operating scenario but with the PLL (phase-locked loop) enabled. Active power draw is at 420 mW with an operating scenario using a 1.2V core running at 300 MHz; the McBSP (multichannel buffered serial port), SPI (serial-peripheral interface), and general-purpose I/Os active; and 50% access of the 16-bit mobile DDR at 133 MHz. These power-consumption numbers represent one-third the power consumption of the previous floating-point devices with a 20-times improvement in the standby power.

TI slates the availability of the other next-generation low-power families for 2009, and they support similar power-consumption numbers with similar operating scenarios. The C640X devices deliver twice the processing performance of the currently available low-power DSPs. The C550x devices halve the low-power operation to 6.8 μW in deep-sleep mode, 0.34 mW in standby mode, and 18 mW in active mode using a 1.05V core running at 60 MHz with 75% DMAC (direct-memory-access-controller) usage and 25% addition operations at normal operating temperature. Active power consumption for a 1.3V core running at 100 MHz with 75% DMAC usage and 25% addition operations at normal operating temperature.

© 2009, Reed Business Information, a division of Reed Elsevier Inc. All Rights Reserved.