TI driving development, ratification of IEEE 1149.7 embedded system standard

By Ann Steffora Mutschler, Senior Editor -- 9/2/2008

To allow developers to easily test and debug products with complex digital circuitry, multiple CPUs and applications software in products such as mobile and handheld communication devices, Texas Instruments Inc (TI), a key member of the IEEE working group, said today that it is spearheading the effort to ratify the IEEE 1149.7 standard, which is a new two-pin test and debug interface standard that supports half the number of pins of the IEEE 1149.1 technology.

The company said that as designers add new functionality to chips and system designs evolve away from boards and toward multi-chip system-on-chip (SoC) architectures, developers of handheld and consumer electronics are faced with stricter pin and package constraints. As such, TI said it is working with Freescale Semiconductor, Intel Corp, Lauterbach Datentechnik, IPExtreme, ASSET InterTech, Corelis and GlobeTech Solutions to refine and identify implementation challenges, meant to ensure a streamlined and robust solution is ready for industry wide adoption.

Specifically, the IEEE 1149.7 is a complementary superset of the widely adopted IEEE 1149.1 (JTAG) standard that has been in use for more than two decades and is scheduled for ratification early next year.

The new standard is meant to serve as a port into embedded systems for device manufacturing, testing and software development during system development, and while it maintains compatibility with IEEE 1149.1, the new standard improves debug capabilities and reduces SoC pin-count requirements, also standardizing power-saving conditions, simplifies manufacturing of multi-chip modules and stacked die devices, providing the ability to transport instrumentation data, TI explained.

“The IEEE 1149.7 test and debug technology will be a milestone for the electronics industry by allowing engineers to easily update their current designs to the new standard while preserving investments and compatibility with existing IP modules and tooling. TI is joined by leading companies such as Freescale, Intel and STMicroelectronics in the industry-wide adoption and integration of this technology into our products,” said Stephen Lau, emulation technology product manager at TI, in a statement.

With a majority of today's systems integrating multiple ICs and often have stringent size constraints, reducing the number of pins and traces is expected to help designers meet their smaller form factor goals and allow for additional functional pins and/or lower package cost. And compared to the four pins reserved for IEEE1149.1, TI said the IEEE 1149.7 uses only two pins to handle clocking, control and data I/O.

The lower pin-count configurations is meant to simplify stacked-die configurations and decrease costs by eliminating the need for additional pins, thus facilitating smaller device form factors while compatibility with existing IEEE 1149.1 devices and IP is aimed at allowing designers to smoothly transition to IEEE 1149.7 without incurring additional costs.

“Reducing pin count is an important technology to enable advanced mobile devices. IEEE 1149.7 is a standardized, reduced pin interface which is compatible with existing technologies and addresses multi-chip debug challenges. This is why IEEE 1149.7 is recommended in the MIPISM test and debug specifications,” noted Rolf Kuhnis of Nokia, and chairman of the Mobile Industry Processor Interface (MIPISM) test and debug working group.

In addition, TI said the new standard provides powerful extensions to the IEEE 1149.1 meant to address SoC architecture challenges, such as scan performance in cards with multi-core devices, power domains, varied device connection topologies and background data transfers.

For higher performance of multi-core applications, the IEEE 1149.7 has a chip-level bypass mechanism to shorten scan chains, to improve the debugging experience. For power sensitive applications, especially handheld devices, four power-down modes are provided to assist engineers during board and chip testing and applications debugging, while a star topology is meant to complement the standard serial topology to allow designers to manage multi-chip architectures with simplified physical inter-device connections, while background data transfers provide a method to send instrumentation data, increasing visibility into SoC devices.

TI expects the IEEE 1149.7 to be ratified in Q1 2009.

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