Designing very high-frequency signal generators with amplifier ICs

By Márian Štofka, Slovak University of Technology, Bratislava, Slovakia -- 10/27/2008

Oscillators and pulse-generators using operational-amplifier ICs have been proposed by many authors. Such generators can be found in a flood of articles in journals, magazines, books, and IC datasheets. Their upper operating frequency scarcely exceeds the value of 10 MHz. Designers can increase the operating frequency of signal generators by using high-frequency operational and RF amplifiers having bandwidths exceeding 1 GHz. The design of these oscillators and pulse-generators is fraught with peculiarities which were not encountered in previous designs. This article will provide examples of a pulse-generator and two designs of a Wien-bridge oscillator.

LC (inductance-capacitance) and RC (resistance-capacitance) oscillators differ in many aspects. An LC tank is apt to oscillate upon being connected to a voltage or current-source. Such an effect never occurs in a passive RC network. The oscillations in an LC tank are damped by losses. In other words, their amplitude tends to zero in time. In an LC oscillator, an active device compensates for the power losses of the LC tank. The demands for this active device are relatively mild. The frequency of oscillation is given primarily by the resonance frequency, which is inherent to the LC tank (Equation 1). While a harmonic signal appears in an RC oscillator, the stand-alone RC network doesn’t exhibit any oscillatory behavior. The reason is that an RC oscillator is a system where a feedback is routed from the output of an amplifier to its input. Harmonic oscillations appear in this system when some conditions are fulfilled. One of these conditions is a gain requirement. An input signal, derived from the output signal via the feedback network has to be the same amplitude as the output, or somewhat higher, when multiplied by the gain of the amplifier. Secondly, the phase of the input signal added with the phase-delay of the amplifier, must give zero value. In contrast to the gain-condition, no “somewhat” is allowed in the phase requirement. In addition, the phase-condition has to hold true for only a single value of frequency. If so, a harmonic signal appears at the output, having the frequency equal to that single frequency.

(1)

SMD (surface mounted device) inductors in VHF band oscillators are limited by several factors. These inductors have a core, most commonly made of a ferromagnetic material, or ferrite. Ferromagnetic particles having a diameter of tens of nanometers; mutually isolated and then compacted to a core, can be used. Due to their higher price the latter cores are not popular. In general, inductors with a core are relatively lossier devices than high frequency SMD capacitors. Ferromagnetic resonance is another limitation of these cores. At a frequency of around 1 GHz to about 3 GHz the movement of electrons at outer shell of an atom gets into resonance with the external magnetic field. The magnetic properties, which were good at lower frequencies, break down. On the other hand, the core-less inductors are also lossy at high frequencies due to the skin-effect in the conductor. The core-less inductors also radiate out more electromagnetic power. Non-radiating cavity resonators are too bulky as compared to the size of an IC.

Capacitors have relative permittivity (ε_r) of up to 10 and can operate at frequencies of 4 to 6 GHz. The higher the value of ε_r, the less space is occupied by the capacitor. The radiating of electromagnetic power at the boundaries of the electrodes of a capacitor is lower at higher value of ε_r. Further, a HF capacitor is much closer to an ideal passive device in comparison to an inductor. In addition to titanium dioxide, there are advanced dielectrics such as hafnium dioxide, zirconium dioxide, and ternary compounds like zirconium silicate. All have a ε_r considerably higher than 1. The key parameter of these dielectrics is quantified as “tangent delta” or loss-tangent at the frequency of interest. The lower value of tgδ, the better. A value of ε_r higher than 1 might be misleading. If the imaginary component of a complex ε_r is prevailing – such a capacitor is almost of no use in RC signal generators, as the equivalent parallel resistor dominates in the impedance.

For HF and VHF oscillators the RC types are used almost exclusively. RC types of generators offer much less susceptibility to stray magnetic fields. RC types are advisable for oscillators and signal generators comprising an amplifier IC and SMD passive devices if there are demands such as small size and low EMI (electromagnetic interference). Signal generators based on DDS (Direct Digital Synthesis) have internal complexity much higher than any IC amplifier. The DDS-based generators have a higher price and consume more power. Therefore, with moderate demands for frequency-stability, RC oscillators are advisable.

A 40 MHz Wien-bridge oscillator

Figure 1: Click here for larger image

The Wien-bridge oscillator has been used for almost seven decades. The active devices used in this circuit are becoming faster, and smaller. You can find the basics of this type of oscillator in many encyclopedias of electronic circuits The word of “Bridge” in the name of a classical Wien-bridge oscillator stems from the fact, that the differential inputs of an amp are tied to the diagonal of the bridge, while the output of this amp drives the bridge (Figure 1a). The op-amp in the figure is drawn in the vertical position to better see the bridge character of the oscillator. The left arm of the bridge is formed by resistive voltage-divider of Ri, RFB. It creates a negative voltage-feedback for the op-amp. The right arm of the bridge, formed by the voltage-divider comprising R₁, C₁ and R₂, C₂, forms a frequency-dependent feedback, which is positive under the oscillatory condition. For the desired oscillation frequency, the phase of voltage at non-inverting input of the amp must be zero with respect to the phase of V_OUT. The magnitude of the voltage at the non-inverting input at the same time is some fraction of V_OUT. For the most common case of R₁=R₂=R, then C₁= C₂=C, therefore the fraction is 1/3.

In addition, let the ratio of the left-arm resistive divider be the same fraction as in the previous point, 1/3 for the case of R₁=R₂=R; C₁=C₂=C. The result is a harmonic voltage at the output of the amplifier, having the frequency given by equation 2. For the case where R₁=R₂=R; C₁=C₂=C, then equation 2 reduces to equation 3. The explanation of why the output voltage is a harmonic one stems from the fact that the zero-phase condition is fulfilled for only a single frequency.

(2)

(3)

Theory states the amplitude of V_OUT to be indefinite, as the circuit in Figure 1a is a linear one. In practice, however, there are limits between zero and the supply or output-saturation voltage. To insure the amplitude is limited to some upper value, let the ratio of the resistive divider be 1/3(1- δ), where δ is a small, positive fraction of 1, such as 0.01.

When the desired oscillation frequency is a significant fraction of the transition frequency of the amplifer, the oscillatory condition of φ_R,C=0 is no longer valid. The transition frequency is a frequency at which the magnitude of the gain of amplifier drops to value of 1. Despite the fact, that the phase of the resistive divider Ri, RFB still may be zero, the amplifier exhibits a phase-shift between its non-inverting input and output. This phase-shift of φ_Closed has a negative sign, as the output of an amplifier is delayed in time with respect to its non-inverting input. The corrected oscillatory phase-condition is φ_R,C+φ_Closed=0. Therefore the phase-angle of the (R,C) arm of the Wien-bridge has to have a positive value, of a magnitude of |φ_Closed|. The coupling capacitor C_C has to be of value of at least 200 times that of the C₁ capacitor. The C_C is not an inevitable component in the circuit and you may replace it by a short. On the other hand, including the C_C cuts the dc-offset and the LF noise to about one third.

Procedure for designing the HF Wien-bridge oscillator

The circuit analysis and design are made for R₁=R₂=R; C₁=C₂=C, which has a consequence of R_FB ~=2Ri, Acl ~=3.

A.   For the desired frequency f of oscillation find the phase-delay φ_Closed of an amplifier, built around the selected op-amp with added negative resistive feedback comprising the resistor R_FB ~=3Ri and the resistor Ri according to the equation 4. Where a=A_c1/A₀, C₁ is the equivalent parasitic capacitance of the voltage-limiting device placed in-parallel to R_FB; Acl ~=3,t_||=C₁ (R_FB || Ri)=1/4C₂R_FB; Ri=1/3R_FB; w=2πf. A₀ is the open-loop dc voltage gain of the op-amp. F_c1, f_c2 are the first and second corner frequencies in the open-loop gain-frequency characteristic of the op-amp. The formula is usable in direct form only until either the denominator or the numerator in the expression changes their sign to -1. If only the denominator is negative, the true phase is obtained from (1) by adding -π radians. Note the warning at the end of this section.

(4)

B.   The (R,C) arm of the Wien-bridge has to create the same magnitude of phase of voltage at its (R₁||C₁) part, as determined in step A. To achieve this, it must hold at the desired frequency given by equation 5, where φ_R,C = |φ_Closed|. The value of C₁=C₂=C is then evaluated from the value of wRC obtained from equation 5.

(5)

An example:

For the desired frequency of f = 44.44 MHz; for the AD8045 op-amp having A₀=1513, f_c1=0.24 MHz, f_c2=330 MHz [1], while Ri=330Ω, R_FB=1 kΩ, C₁ ~=1.2×10^-12 F, R₁=R₂= R=330Ω, we get for step A:

φ_Closed ~= -37.2

In step B by inserting this value into (5) we get: wCR=0.3768

Figure 2: Click here for larger image

Contrary to dozens of paperback textbooks advising that wCR=1, we get a much more accurate value of capacitor needed: C=0.37868/wR=4.09×10^-12F Using the capacitors C₁=C₂=C=4.7 pF in the circuit, you obtain an output (Figure 2). If you had used the formula wCR=1, you would get oscillations at below the desired frequency. As can be seen, there is a small difference between the calculated and the used values of C. Moreover, the AD8045 input capacitance C_IN=1.3 pF, acts in parallel with C₁. The actual value of a capacitor in the parallel part of the (R,C) arm of the Wien-bridge is therefore: C₁’=C₁+C_IN=6 pF. These differences are, however, still negligible in comparison to those, you would have obtained by using the formula wCR=1.

Warning:

From formula (5) it follows that if frequency f is desired, and the phase-delay of your amp approaches the value of –π/2 radians, any attempt to construct a well-defined Wien-bridge oscillating at a frequency f are in vain. In such a case select another op-amp having a much higher gain-bandwidth product. The same holds true, if the magnitude of the phase-delay of the amp exceeds the value of π/2 radians.

30-MHz pulse generator has rise and fall times of 3 nanoseconds

Internal circuit diagrams of op amps are not given in datasheets. That’s a pity, because even a medium-detailed scheme may carry information, which is not contained in the tables, nor in the accompanying text. There is also a class of datasheets with a simplification of the circuit diagram of a described IC. The datasheet of the Analog Devices’ AD8099 amplifier (Reference 3) belongs to that class. The circuit diagram is a cascade of symbols for an input differential amplifier and a buffer. The input of the buffer is accessible externally at one pin of the IC. A recently published design idea (Reference 4) sheds some light on the character of outputs from this type of input stage. From comparison of Figure 2 and Figure 3 in (Reference 3) it can be seen that by loading the C_C pin of an overdriven AD8099 with a current of plus/minus 6 mA, the voltage span at C_C pin shrinks from ±3.85V to ±2.95V. The output of the input stage (pin C_C) has a characteristic of a voltage-source with an output resistance value 150Ω (Equation 6).

(6)

Figure 3: Click here for larger image

The pulse generator is based on an AD8099 op amp. The clamping circuit does not require any external reference voltages (Figure 3). Here the reference voltages of ±1.25V are derived by using two precise, ground-referenced, band-gap voltage cells of IC₃, which are supplied from the op amp’s supply rails. The path from ground through the 47 nF decoupling capacitors and through two Schottky-barrier diodes in IC₂ and through resistor RC to C_C pin of IC₁ is as short as possible. The clamping circuit is thus very fast-acting and no transient spikes appear after level-transitions at the output of op amp (Figure 2). The output voltage waveform is roughly a rectangular one with the duty-factor of approximately 0.5.

Analysis of level-transitions in the output voltage

The steepest part of the output voltage waveform is crossing zero-volts. Here the two Schottky-barrier diodes used within the Avago’s HSMS-282L trio of IC₂ are reverse-polarized, both at Vr=1.25 V. The maximum capacitance of a diode in the HSMS-282L is 1 pF at zero voltage. The typical value is 0.7 pF (Reference 4). This capacitance monotonously decreases with reverse voltage and at Vr = 1.25 V it can be estimated as 0.8Cj~0.56 pF; where Cj is the capacitance at zero voltage. Thus the sum of capacitances of both diodes is 1.12 pF and represents an external capacitor connected to pin C_C of IC₁. The slew-rate of IC₁ decreases with capacitance connected to pin C_C and the function describing this dependence is an inversely proportional one, having the form of equation 7.

(7)

SR₀ is the value of slew-rate at zero external capacitance C_C. In Table 4 in Reference 3 it can be found, that for gains of 10 and higher, the slew-rate drops by 100 V/μs per 0.5 pF addition of C_C. From these data the constant C₀ can be determined as C₀=6.75 pF. C₀ represents an internal capacitance of IC₁ at pin C_C. The expected slew-rate of IC₁ in the generator in Figure 3 is from solving equation 7 as shown in equation 8:

(8)

The slew-rate of AD8099 rises with supply voltage. One can, by comparing the tables 1, 2 and 4 in Reference 3 postulate an empirical formula for the slew-rate as a function of supply voltage at high gains (higher than 20) shown in equation 9.

(9)

Figure 4: Click here for larger image

It is assumed, that the +V_s and -V_s supply voltages have the same magnitude. For a ±3.8V supply; for instance, it follows from equation 9 that SR₀=1122.6 V/μs. If we now take into account slowing-down due to a nonzero value of the C_C capacitor, we get, by using equation 7, SR_CC=962.8 V/μs. This value is in good agreement with experimental data, given in Figure 4.

The experimental data, given in Figure 5 shows, that the frequency f of the generated waveform rises with supply voltage, with a maximum steepness of about 3.87 MHz per volt. In a simplified theoretical model of the generator, the frequency f should be held constant at varying the supply voltage. Such an assumption stems from the fact, that both the charging current of the timing capacitor C_T and the threshold voltage of the IC₁ comparator are derived from the same output voltage. In practice, however, due to rising steepness of the triangle-like wave-shape on the C_T capacitor with rising V_s, the signal-propagation delay of the IC₁ comparator decreases. As a consequence, the length of period of output signal becomes somewhat shorter. 

Figure 5: Click here for larger image

Theoretical analysis of slopes of output waveform

The voltage transfer-function of an uncompensated AD8099 can be derived from Figure 14 in Reference 3 as equation 10. Where A₀=20,000 is the dc gain; τ₁ ~= 7.234×10^-7s and τ₂ ~=5.684×10^-10s and are the time-constants, corresponding to the first break point and the second break point, respectively, of the gain-frequency characteristic.

(10)

The voltage transitions of V_OUT were analysed for a simplified model of the generator. Here the parasitic parameters of a differential input capacitance of 2 pF and the differential input resistance of 4kΩ of the op-amp were neglected. Parasitic capacitances, parallel to each of the resistors R_T, R₁, R₂, were neglected as well. For the sake of simplicity, the current charging the capacitor C_T through the resistor R_T was considered to be constant, as the voltage swing on C_T here is one third of that of.output voltage. Finally the time-constant τ₂ , which is impressively small (within a sub-nanosecond range) has been substituted by zero in equation10. The result of analysis is then in the form of equation 11. Where V_OUTm is the amplitude of the flat part of the output waveform; α is the ratio of R₁/( R₁+R₂) of the positive feedback. Note, that the exponent in equation 11 is positive, denoting an avalanche-like character of the transient phenomenon. From equation 11 the slope of the output voltage transition can be derived, while its value at t=0 is given in equation 12:

(11)

(12)

The instant of t=0 is when the voltage on C_T reaches a value equal to that, which persisted at non-inverting input of IC₁ within the preceding flat part of the output waveform. By evaluating equation 12, the initial output slope should be of about 8.8×10⁹V/s. This value exceeds the value of slew-rate of IC₁ by a factor of about 8. The time function of equation 11 is therefore true for small only values of α, or much lower thresholds in hysteresis due to positive feedback. Despite this negative aspect, the above analysis allows you to make the following clear conclusions: Firstly, the transitions of the output voltage are performed at the actual slew-rate of IC₁. Secondly, these transitions start immediately upon the zero-crossing of the differential voltage at the inputs of IC₁.

The Virtue of a differential input capacitance on the operation of the generator

The differential input capacitance C_INdiff ~=2 pF of IC₁ is ground-referenced through the parallel combination of the resistors R₁, R₂, where R₁||R₂, =320Ω. The corresponding time-constant of τ_IN=C_INdiff(R₁||R₂) ~=0.64 nS. is negligible, as compared to half-period of the generated waveform Tout/2 ~=15 nS. The voltage on the C_INdiff follows approximately the voltage on the C_T within the flat parts of V_OUT, with a relative difference shown by equation 13. This 10% decrease can be neglected here and the C_INdiff is further taken as a part of the timing capacitor, having the total value of C_T+C_INdiff.

(13)

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References

"AD8045: 3 nV/ Ultralow Distortion, High Speed Op Amp," Analog Devices, Inc, 2004.  "Surface Mount RF Schottky Barrier Diodes," Avago Technologies. "Ultralow Distortion, High Speed 0.95 nV Voltage Noise Op Amp AD8099," Analog Devices, Inc, 2004. J. Ardizzoni, "Clamping Circuit Lowers Distortion, Improves Overdrive Recovery Time," Electronic Design, June 21, 2007. Author Information  Marián Štofka is with the Slovak University of Technology, Bratislava, Slovakia.

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