Power SOCs: A “crazy” idea that just might work

Imagine a cell-phone battery that could supply unlimited power and still fit into its current form factor: the perfect solution to the biggest drawback in today’s portable electronics, right? Wrong. Even with this magic battery, you’d still have the problem of power dissipation: With today’s power-management schemes, a cell phone would quickly become too hot to handle. It’s about efficient power, not available power. In the search for increasingly efficient power schemes, the concept of a power SOC (supply on chip), including power conversion, regulation, management, and passive components, has emerged as the Holy Grail. Some power companies and university researchers are on the quest. Power SOCs would benefit not only handheld electronics, but also laptop computers, which would enjoy extended battery life, and servers, which would have lower energy costs. These power SOCs will appeal to virtually every type of electronic application in the coming years.

Today’s dc/dc PMU (power-management-unit) ICs with external inductors are already much smaller than their predecessors of just a few years ago. For example, Analog Devices’ 6-MHz ADP2121 switcher, which relies on an external inductor, takes up only 5 mm², including the inductor. The proliferation of cores within today’s ASICs is the driving force behind the need for further reducing power-control circuitry into a power SOC. For example, a cell phone might have four or more antennas, including Bluetooth, CDMA (code-division/multiple-access), GSM (global-system-for-mobile)-communication, and 3G (third-generation) units, as well as video and baseband-RF sections. To ensure power efficiency, each core must quickly turn on or off; otherwise, the system would waste power on a core that’s not in use. For fine-grained power control, each core needs its own dc-voltage source, including voltage conversion and regulation. Yet, four or more PMUs hanging off a multicore chip would dwarf the chip, even if they each measure only 5 mm².

You may consider sprinkling a few power-supply modules on the board and using semiconductor switches to turn the cores and subblocks on and off. However, it’s difficult for a power supply to remain efficient over its entire load range—typically, 10 to 90%. A master power supply that spends most of its time in a low-current-load range would yield less power efficiency and more system heat.

Power-SOC technology faces two major deficiencies: efficient, cost-effective switching devices and magnetics operating at 20 to 100 MHz or more. True, ultrahigh-speed switching devices exist in the RF realm, but their developers usually base them on exotic semiconductors, rather than inexpensive silicon processes. Designers have also developed magnetics for the RF world, but their purpose has been to radiate power. A power-supply application requires the exact opposite: quiet, nonradiating devices. In addition, magnetic research has been relatively sleepy: As long as high-speed switching devices were impractical, no one needed high-speed magnetics.

Cian Ó Mathúna, PhD, a researcher in power magnetics at University College Cork’s Tyndall National Institute, predicts that complete power SOCs, including an integrated inductor, will soon be able to fit into a footprint of only 1 mm², including the wafer-scale miniaturized inductor on a power-control wafer inside a PSIP (power system in package). From a BOM (bill-of-materials) point of view, there’s little difference between a PSIP and a power SOC: If you split a PSIP open, you’ll see the silicon switching devices and control circuit in one IC and the magnetics and capacitors in one or two other devices—all in one package. Although PSIP devices don’t take advantage of the cost reduction and added reliability of wafer-level fabrication, they do meet applications’ needs for small parts, simple design, reduced BOM costs, and simpler assembly. Several analog companies, including Vicor, Linear Technology, and Enpirion, have begun to employ this approach.

For example, Enpirion’s 1-MHz, 600-mA EP5368Q integrates an inductor, fits into a 3×3×1.1-mm QFN package, and has total dimensions as small as 22 mm², including two external capacitors. The company offers a range of devices that provide as much as 9A and switch at speeds as high as 5 MHz. Enpirion separates the switching and control circuitry from the inductor and places the two die in one package. The company may fabricate the inductor on a silicon wafer or in more traditional multilayer spirals, depending on the application’s requirements, according to Michael Laflin, director of product marketing for the company. Those requirements include such factors as load current, inductance, loss budget, and saturation current. The company also takes into account the fact that different magnetic materials exhibit different loss characteristics and behaviors at different frequencies, so magnetic materials also have a part in the inductor-design equation. Enpirion is not forthcoming about the technology behind its inductors because magnetics technology is the “secret sauce” in its devices.

In a paper that Enpirion presented at the PwrSOC (Power-SOC) Workshop last January in Cork, Ireland, the company detailed the lessons it learned in manufacturability, yields, reliability, and cost (Reference 1). These prosaic determinants are the keys to developing successful products because, in power management, says Laflin, “cost drives everything.”

One of the most experienced research centers for wafer-scale magnetics, the Tyndall National Institute at Ireland’s University College Cork uses its 4-in.-wafer line for research in inductors switching at 10 to 100 MHz (Figure 2a). These inductors use a “racetrack” geometry of electroplated copper windings encased in a thin-film, electroplated, enclosed, nickel-iron, soft-magnetic core (Reference 2). As a reference point, Tyndall researchers demonstrated the inductors operating at 15 to 65 MHz with a monolithic MOSFET and driver-power-train IC. The efficiency for this buck-converter SMPS (switched-mode power supply), including both the converter and the inductor, was 80% at 20 MHz using a commercial chip inductor from Coilcraft and with input voltage of 3V, output voltage of 1.5V, and output current of 100 mA. When researchers substituted the Tyndall 2.5-mm² microinductor, the efficiency decreased to 76%. Keep in mind, however, that the Tyndall inductor was not designed for the circuit, as it would have been in a production design. According to Ó Mathúna, the researchers can tweak both copper and core losses. “We’re electroplating copper windings into a mold to a thickness of, say, 35 to 50 microns,” he says. “If we go to a higher thickness of copper, we would be able to emulate to a large extent the Coilcraft inductor. In addition, the magnetic-core material has its own inherent losses. In thin-film-plated magnetic materials, that resistivity is going to be very low—that is, those materials are going to be quite conductive. For example, a nickel-iron material has a resistivity of about 45 µΩ-cm. If we move to another magnetic material with closer to 100 to 150 µΩ-cm, we could reduce the eddy-current losses.”

The other sticking point in power-SOC development is the high-speed switching device. The buck-converter architecture, currently the most common dc/dc-SMPS topology, has a negative relationship between efficiency and switching frequency: With each increase in switching frequency, efficiency initially falls. “If your design is switching at 5 MHz and you increase it to 20 MHz, you’ll have at least four times more switching loss,” says Ted Thomas, product-line manager for Texas Instruments’ power-management products. “Switching loss ends up dominating the efficiency of the power supply.”

However, several topologies have a less stringent relationship between switching frequency and inefficiency. For example, with a ZVS (zero-voltage-switching) topology, the switching device turns on and off only when there is no voltage across it. You use the circuit’s resonant frequency to determine the zero-voltage point. Designers have for years used ZVS in ac/dc-power supplies, which must accommodate large currents. The problem with these low-switching-loss topologies is their complexity. If manufacturers could package them in “black-box” power SOCs with the appropriate magnetic components for the design, however, they could become straightforward building blocks for circuit designers.

Technologies employing nontraditional processes are other options now open to designers exploring faster switching devices. For example, silicon carbide can support high switching rates with relatively low losses, but its relatively high cost may rule it out for mainstream, cost-conscious devices. Last September, International Rectifier announced its gallium-nitride platform, a semiconductor process that the company touts as having game-changing higher power density. The company claims that its technological advantage lies in its ability to use inexpensive, readily available silicon wafers to build circuits. This approach lowers cost without sacrificing performance. The devices can also switch at much higher voltages than nonsilicon gallium-nitride products. International Rectifier plans to begin shipping samples of the devices, which operate at less than 6 to 10 MHz, by year’s end.

What else is in the future for power SOCs? Look for 10- and 100-MHz PSIPs, both on standard silicon processes, to emerge within the next 18 months and three to five years, respectively.