"In-design" physical verification is "on-time" physical verification

By Sanjay Bali, Synopsys Inc. -- 5/11/2009

Physical design engineers who create chips at the 45-nm node and beyond face a difficult task. The time-tested flows used at previous nodes are no longer viable to maintain productivity at today’s advanced nodes. Historically, physical design engineers completed design blocks, perhaps even the entire design, then checked them using the fast router-based physical verification check. If any errors were

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detected, the physical designer would repair the problem and verify once again. The clean design was then handed to the physical verification team for sign-off validation. The small number of errors present in the design could be fixed in engineering change-order (ECO) fashion by streaming the design back into the place-and-route environment, repairing the error and streaming out for another round of physical verification. Though cumbersome, this flow was manageable, and somehow provided physical designers with a means to generate a sign-off-qualified design.

For a number of reasons, the “implement-then-verify” flow described above is no longer viable at 45 nm and beyond. The first problem is the complexity and size of designs at 45 nm, which magnify the difficulty of the physical verification process. Design size continues to increase unabated, stressing existing physical verification solutions and demanding new methodologies to process ever-increasing quantities of design data. Another problem is the large number of design rules required for sign-off; more than 1000 design rules must be validated to fully qualify a design for manufacturing sign-off at 45 nm. The complexity of the rules has also increased as the impact on a given structure is no longer limited to its nearest neighbor. In an effort to capture these effects, far too many complex rules exist to be effectively checked by lightweight router-based physical verification. A third problem is the nature of the 45-nm process, which demands a comprehensive design-for-manufacturing (DFM) treatment that includes metal fill, via fill, and other countermeasures to increase manufacturability. Track-based metal fill, which was adequate for past nodes, cannot meet the complex DFM requirements at 45 nm and beyond. A final problem is the point tool-driven, de facto stream-in and stream-out flow used for physical verification, which is becoming more time-consuming as the design size increases. For the above reasons, the traditional implement-then-verify flow must change to meet the needs of physical designers working at today’s leading-edge process nodes.

It's time for implementation and physical verification to come together. This integration will support a verify-as-you-build methodology, keeping late-stage corrections to a minimum. The cost of correcting physical verification problems at 45 nm and below is prohibitive. The only way forward is prevention of these problems, which can be done by running physical verification as early as possible during implementation in quick, inexpensive loops. This integration of physical design and physical verification will enable “in-design physical verification.”

The prerequisite for the in-design physical verification flow is a fast, super-scalar, sign-off-quality physical verification engine. Sign-off accuracy is required to fully cover the complex design rules and DFM requirements at 45 nm, and to avoid costly fixes late in the design flow that may have risen due to lack of sign-off accuracy in physical verification. For example, complex rules that cover litho-related issues, such as end of line and minimum edge conditions, are now commonplace at 45 nm. The engine must also be high performance and scalable in order to handle the rule and design size complexities. Processor clock speeds are not getting any faster, and multicore technology is now the mainstream technology for boosting the performance of compute-intensive applications. To take full advantage of multicore, the engine must be natively architected to scale linearly across the existing compute network, without custom configuration or special runset setup.

In-design physical verification can enable several high-productivity flows. One such example is in-design DRC checking. Integration will offer sign-off-quality DRC checking while in implementation, enabling physical verification as early as possible in the design flow. For example, power grid opens, shorts, or standard cell fill errors found late in the design cycle can lead to project scope creep or delayed time to tapeout, as changes to placement and routing would likely be required. The in-design physical verification will eliminate such costly violations. This solution with automation will further enhance productivity for physical designers by offering an auto-interactive find and fix verification solution. In addition, having an integrated sign-off-quality verification tool will complement the router. Corner case rules take a significant amount of coding effort, and result in a performance penalty in the router. This integration will enable a complementary flow in which the physical verification tool can provide guidance to the router on these corner case rules, allowing the router to focus on fast, convergent design closure. Given the explosion in design size, the divide and conquer approach is a must-have feature to enable high productivity. A solution where physical verification can be done on a layer basis or rule basis will allow quick, early physical verification, thereby ensuring that physical verification at the full chip level will proceed smoothly. In-design physical verification is thus a critical capability that will ensure a correct-by construction design and enable faster time to tapeout.

There are practical aspects of DFM that are becoming integral to design implementation. Metal fill for planarity is one such example of practical DFM. This integrated in-design physical verification solution will afford such DFM flows. The integrated solution will support timing-driven sign-off-quality metal fill that uses trackless metal fill patterns for optimum pattern density, better design planarity, and higher design yield. The fast execution inherent in the in-design flow allows designers to quickly insert sign-off-qualified fill in a single pass and improve time to tapeout.

In summary, designers working at 45 nm and 32 nm need prevention due to the prohibitive cost of correction. The minimum requirement is a sign-off-quality physical verification engine architected for in-design physical verification; that is, one with low overhead to run alongside with place and route. With this integration, physical verification becomes integral to every place and route run, thereby avoiding excessive iterations between physical design and physical verification in today’s flows. The result will be faster time to tapeout and better DFM.

Author Information

Sanjay Bali is director of product marketing in the Implementation Group at Synopsys. With more than 15 years’ experience in the semiconductor industry, including several in EDA, he is currently responsible for Synopsys’ physical verification and DFM product suite, which includes Hercules and PrimeYield. Bali holds a master’s degree in computer engineering and a master’s degree in business administration from Santa Clara University.

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