Sine-wave generator outputs precise periods

JM Terrade, Clermont-Ferrand, France -- 4/26/2001

Rectangular pulse generators, even at high frequencies, are easy to design. However, the design becomes more difficult if you need a signal that contains a precise number of periods with a sinusoidal shape. Although it is easy to produce a good sine wave, the difficulty is producing a signal with a precise number of periods. The signal has to start and stop exactly at 0V. The scheme in Figure 1 can produce one to 15 periods of a 20-MHz sinusoidal wave. The scheme has two main characteristics: The positive edge of a 5V signal triggers the input, and the output is one to 15 periods of a 20-MHz signal, adjustable to within ±10%.

Initially, the trigger input is inactive, the generator is disabled, and the counter is loaded with the number N. When the trigger input becomes active, the counter waits, and the end-count output enables the generator. A sine wave appears at the output. At the end of each period of the sine wave, the comparator produces a sync signal that drives the counter's clock input. When N periods of the output wave have occurred, the end-count signal disables the generator.

In the actual circuit, a MAX038, IC₁, is the generator (Figure 2). This IC contains the sine-wave generator and the comparator. The sync signal is available at Pin 14. The counter has to be fast enough to stop the generator before the next output period starts. The 74AC191, IC₂, is a 4-bit up/down counter with preset inputs. NAND gates IC_3A and IC_3B disable the counter after the end-count goes active. A one-shot circuit, IC_5A, ensures that the input trigger pulse is long enough to allow 15 pulses. A MOS switch, IC₄, short-circuits the oscillator capacitor, C₁, to stop IC₁'s generator. If the circuit simply grounds C₁ to stop the generator, the output voltage is not zero. To obtain a zero output voltage, the circuit connects input Pin 5 of IC₁ to a negative 0.5V-dc voltage generator comprising an LF356N and associated components.

Because the signal at Pin 5 of IC₁ goes positive and negative, IC₄'s switch requires a ±5V supply. The level for the command signal also has to swing positive and negative. MOS transistor Q₁ provides the level-shifting from 0 to 5V logic levels to ±5V, or 4016, logic levels. NAND gates IC_3C and IC_3D allow a fast drive for Q₁.

The circuit's operation consists of three timing periods: load N with trigger input inactive, down-count with trigger input high, and disabled (Figure 3). When the trigger input is inactive, one-shot IC_5A is inactive. The level at Point B in the circuit is low, and counter IC₂ is continuously loading the number N that you program using S₁. The level at D is high, and the counter can't run. The voltage at C is low. The circuit connects NAND gates IC_3C and IC_3D in parallel to provide more current to drive Q₁ faster during switching. C₂ is also necessary to drive Q₁ faster. These NAND gates invert the level at D, and Q₁ is on, driven with 0V through R₁. Thus, a 5V level is present at E, and the IC₄ switches are on. Potentiometer R₃ controls the voltage at G; the LF356N acts as a voltage follower. The 10W resistor, R₂, prevents oscillations during switching. C₁ and the MAX038 input represent the charge impedance. The four switches of IC₄ connect in parallel to present a lower resistance of 200W/4, or approximately 50W, of total resistance. The switches apply the voltage at G to Pin 5 of IC₁, which stops the internal oscillator. The levels at the signal output and at the sync output, F, depend on the voltage at Pin 5. The voltage at F needs to be 5V, and the voltage at Signal Out needs to be as close to 0V as possible. You need to carefully adjust R₃ to match these conditions. The output voltage is just over 0V when G is close to –0.5V.

When the trigger input goes high, one-shot IC_5A starts running. The voltage at B also goes high for 10 µsec. This delay must be longer than 16 periods of the output signal. The voltage at D now goes low and enables the counter. As before, IC_3C and IC_3D invert the level at D, and the 5V drive turns off Q₁. A –5V level is present at E, and IC₄ switches are off. The internal oscillator of IC₁ is now running, and a signal is present at the output, S. Each time the output signal is positive, the sync output at F is also positive. At the end of each period, a positive-going edge appears at F. Each positive edge at F makes counter IC₂ count down by one.

When the circuit has produced N periods at S, the voltage at C goes high, which indicates end of count. The voltage at D goes high and disables the counter. IC_3C and IC_3D invert the voltage at D, and the resulting 0V drive turns on Q₁. A 5V level is present at E, and IC₄ switches are on. The internal oscillator of IC₁ stops, and the output signal at F returns to zero. Before returning to the original state, the signal at B should return to zero, which happens after the end of the delay that one-shot IC_5A produces.

All is now ready for another train of pulses. Using S₁, you can program the circuit for one to 15 pulses. The circuit can produce other signal shapes, depending on how you connect A₀ and A₁ of IC₁ (Table 1). You can also replace S₁ with a µC to produce any pattern of pulses.

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