Practical Chip Design

TSMC's roadmap announcement for their 28 nm node yesterday has stirred considerable controversy already. The issue is the company's decision to divide their process development into two tracks: one to be ready early using SiON gate technology, and one to be ready somewhat later—and with more schedule risk—using high-k/metal-gate technology.

TSMC justified the decision by claiming that for designs with high duty cycles—meaning that blocks would most of the time be either operating or power-gated off—active power was more important than leakage power. And hence gate capacitance was a more important factor in energy consumption than leakage. Further, the company claimed that their SiON process would have a significantly lower gate capacitance, and hence lower active power, than an equivalent high-k/metal-gate process.

But in comments to a Blog posting describing the announcement, one reader jumped on that claim at once, pointing out several issues that make the conclusion less than obvious. And in remarks during a question-and-answer session at the Common Platform Technology Forum today, IBM Semiconductor R/D Center vice president Gary Patton challenged the notion that a SiON process would have lower active power, or for that matter, that it would even have lower gate capacitance. He said that while the higher k would increase the gate capacitance per unit area, the higher k also allowed transistors to have a shorter effective channel length, so that the capacitance stayed about the same. Others have pointed out that the high-k transistor would either have the same current at a smaller width, so in principle it should have less active gate area, hence lower capacitance, and dissipate less active power at equivalent performance.

An Steegen, senior technology development manager at IBM Systems and Technology Group, agreed that gate capacitance—or more properly, inversion-layer thickness—is a big deal in the whole question of process scaling. But she added that you couldn't just look at gate capacitance in estimating the active power dissipation in a circuit—you had to examine the total circuit capacitance. And once again the smaller minimum dimensions of the high-k transistor make a difference. Smaller transistors allow for denser packing, shortening average wire length between the transistors and reducing the load capacitance. (Relaxed contact spacing due to the shorter channel length is also a big deal for yield, Steegen suggested, since the contact layer is one of the most critical steps in the process now.)

"This is not just a PowerPoint comparison," Patton said. "We have run SiON and high-k/metal-gate devices side by side, and the high-k versions have lower dynamic power."