Practical Chip Design

With a certain inevitability the infrastructure to support mainstream IC design at 45 nm is beginning to appear. Today, Virage Logic will announce it's SiWare libraries in support of TSMC's 40 nm processes. A brief look under the covers at the new libraries shows both how successful the industry was at getting a handle on the new challenges at 65 nm, and how much 45 nm will stress the solutions we chose.

The first thing that strikes one about the new library offerings is the proliferation of options. Virage will cover both the LP and G process variants, of course. But beyond that, there are no less than ten different memory compilers, each of which comes with extensive knobs for tuning area, power, performance, read-write margins, and yield trade-offs. Logic libraries are available at 7, 9, and 12-grids to allow area-versus-performance-versus-yield tradeoffs in each process variant. And there are options for threshold voltage, back-bias, power-gating, and other items. Just the task of choosing a set of compiler parameters and logic libraries for a design is beginning to look a lot more like Chinese watercolor than paint-by-numbers.

Are the libraries themselves fundamentally different? For that you'd have to define "fundamental." Virage VP of product marketing and strategic foundry relationships Brani Buric says that it has become impossible to simply port a physical design from one process node to another. For good results, you have to start over from scratch. So the 45 nm generation of libraries and compilers are not simple modifications of the 65 nm work. But they are not fundamentally different, either.

One specific difference is the amount of effort that has gone into characterizing and understanding process variations. "The memories are the most critical design elements, because that's where we push the critical dimensions," Buric says. "We generate structures from the memory compilers to estimate variations from such process steps as dopant implant, CMP, critical-dimension resolution, and strain formation. And we have modified circuits to, for instance, keep read-write margins in-range, and better control sense-amp stability."

As in other recent Virage offerings there is extensive support for power gating, dynamic voltage control, variable-threshold design, and back-biasing for dynamic threshold-voltage control. "All 45 nm designs will require aggressive power management techniques," Buric observes. "At this node it's not an option."

With such a range of offerings, cells, and options, verification has been a huge task, Buric admits. For instance, in order to support dynamic voltage scaling, Virage has characterized the logic libraries at seven PVT corners per library, and offers further work at customer-defined corners. The memory compilers are also capable of generating structures in which the array runs at a higher voltage from the periphery, preserving margins while saving power.

On the positive side, compilers and libraries for 45 nm don't appear to have required fundamental changes from 65. But on the other side, the amount of work that has gone into providing knobs and options, flexibility for users, power-management tools, and above all silicon verification seems to be growing exponentially. And there is more to be done.

TSMC has only recently announced process freeze. So the libraries will have to be recompiled at least one more time using post-freeze models as they become available from the foundry. In addition, Buric says that Virage is closely watching the needs of early customers to see if the logic libraries, in particular, will have to be characterized for statistical timing tools. That would be another huge data-gathering project, without and standard format for the data—another open-ended commitment.