A couple of weeks ago, I took a pre-briefing from the folks at Mentor Graphics and Cadence Design Systems on their plans to standardize on a jointly developed common SystemVerilog verification methodology called OVM (Open Verification Methodology). They claim the OVM will essentially allow Cadence and Mentor simulators (and any other vendor willing to join the effort) to work with the same implementation (common class libraries) of the OVM verification methodology specification,

“Collaboration,” “co-operation,” “open” and “interoperability” are always words that users and the EDA press embrace. But over the many years I’ve been covering the EDA industry, I’ve come to learn that behind just about every “open standards” proposal in EDA is an ulterior motive—and more times than not, a new “open effort” is simply two or more smaller players trying to gang up and gain share from a dominant player in a given EDA sub- market. (Skill, Libery, Lef/Def, Verilog and VHDL…the list goes on and on).

I suspected that was the case here and shortly after writing up the OVM announcement, I learned indeed it is.

In short, the story between the lines of the OVM story, is that OVM is a direct response to the Synopsys VMM (Verification Methodology Manual) co-authored by ARM, and, more so another battle in what’s revving up to be a gig war for a new bowl of EDA food (to use a Joe Costello’s analogy): SystemVerilog marketshare.

After posting my write up the OVM announcement (essentially reporting the claims of the OVM folks), I heard from both Synopsys and even from Wally Rhines, CEO and Chairman of Mentor Graphics.

Synopsys public relations representative sent me the following note:

“…I wanted to relay a few points around VMM that may have been overlooked around the whole issue of openness with the recent SystemVerilog announcement from Cadence and Mentor:

1. VMM supports transaction-level verification with SystemC.

2. It was jointly developed by Synopsys and ARM with consultation from over 30 user companies and addresses all aspects of functional verification.

3. Synopsys customers have free access to the source code for VMM.

4. VMM base classes are written in IEEE 1800 SystemVerilog standard.

5. VMM is being used on 100's of projects, globally and has been in use for more than two years.”

 Then late last week, Wally Rhines called me directly. Wally had issues with another part of my OVM write-up--the part where I indicate that Synopsys is seen as having the lead in SystemVerilog in part because it acquired Co-Design, the inventor of Superlog/SystemVerilog.

Wally said that Mentor actually had SystemVerilog support in its Questa/ModelSim platform before anyone else did and he said he believes that Mentor has the most customers and the lead in SystemVerilog.

He also noted that traditionally the logic simulation tool market has been evenly split between the big three: with Cadence, Synopsys and Mentor each owning roughly 33% of that market. He notes that in the final year in which Gary Smith was issuing market reports on EDA for Gartner Dataquest, which was for the year 2004, Mentor had jumped into a slight lead in HDL simulation marketshare. He said he believes Mentor has continued to build on that lead in both HDL and SystemVerilog simulation.

Wally conceded he didn’t have any concrete data points to back his assertion that TODAY Mentor has the lead in either SystemVerilog or HDL simulation (Mentor can subtract its own SV simulation revenue from the EDAC simulation marketshare numbers to get an idea of what there share is but using that method they can't tell what their competitors share is). That said, it makes a bit of sense that Mentor would at least have some claim to the lead in SystemVerilog marketshare if indeed Mentor had SystemVerilog support in its simulator before its competitors. So I called Gary Smith…Continued on “Who is the EDA leader in SystemVerilog simulation? Part 2”