Admittedly, my tongue was firmly embedded in my cheek when I posted yesterday's April Fool's writeup on NVIDIA's supposed acquisition of AMD. Underneath the satire, however, was a solid foundation of skepticism about AMD's future. As I wrote at the end of another post in yesterday's series:

The most tempting spoofs are the ones that "could" be true, right?

In mid-December of last year, I published an admittedly downbeat analysis of AMD's fortunes, coming on the heels of the company's mid-September introduction of the quad-core server-tailored Barcelona CPU and mid-November unveiling of the closely related (common die, even? AMD won't say) Phenom desktop PC follow-on. As of last week, AMD is beginning to ship B3-stepping variants of its products, fixing the embarrassing TLB cache bug (discovered shortly before the Phenom launch, and several months subsequent to the Barcelona unveiling) that both limited top speeds and necessitated a performance-strapping BIOS-based microcode tweak. However, for several months to come, a notable percentage of already-in-line Phenom product flowing out of AMD fabs, packaging and test facilities and warehouses will still be "B2" TLB-flawed material, headed to OEMs who are willing to accept the speed-limiting microcode patch workaround.

Next, let's look at the touted triple-core Phenoms that AMD also formally launched last week. AMD first began publicly talking about them coincident with competitor Intel's Developer Forum last September. Given the 6.5 month delay between then and now, I'd hoped that AMD would have designed standalone triple-core silicon with optimized die area (putting, for example, cache in the 'hole' where the fourth core was previously located, as Intel's doing with its upcoming six-core Dunnington CPU, and predating the GPU-for-CPU core swap that AMD will probably implement with its upcoming Fusion products). However, my hopes were dashed when, in response to my last-Thursday query for a triple-core die photo, my AMD technical contact replied:

Sigh. My pessimistic suspicions are confirmed. AMD's shipping quad-core die with one faulty (functional and/or speed) core disabled and, like the quad-core Phenom, much of the material will be TLB-flawed to boot for months to come (note: albeit only to OEMs; as of last week, new triple- and quad-core CPUs flowing directly to retail will exclusively be B3 stepping-based). My AMD contact, in subsequent email and voicemail dialogue, brought up some valid points about the strategy:

• It enables AMD to ship and sell die that otherwise would be performance-hampered or scrapheap-destined by virtue of a single-core deficit, and
• It's a capability with a degree of granularity that only AMD can currently support, by virtue of its CPUs' HyperTransport core-to-core interconnect...although Intel demonstrated working systems based on its competitive QuickPath (aka CSI, for Common System Interconnect)-inclusive Nehalem-generation CPUs two weeks ago, with full production slated for the fourth quarter of this year.

The root of my concern, however, is that AMD has had to go the one-bad-core route at all, and that the triple-core launch was so obviously a last-minute reactive move versus a long-planned proactive part of the Phenom program. In that light, I'm reminded of Paul Otellini's sarcastic comment at last September's IDF:

We see a distinctive advantage in having all the cores on one die work.

Continue reading with 'AMD's Fading High-End Fortunes: Where Will The Rebound Come From?'...

*Do you want to fly, too?