It's been a busy day here at the Intel Developer Forum in foggy San Francisco. When I left Sacramento late afternoon Monday it was nearly 100 degrees and the sun was blazing bright....two hours later, after my train-plus-bus ride here, it was 35 degrees cooler. I don't care if Mark Twain never did say 'The coldest winter I ever spent was a summer in San Francisco", it's still an apt quote (although he clearly never visited Northern Indiana in late January). But I digress...

As predicted beforehand, Intel CEO Paul Otellini rolled out three new (i.e. above and beyond the roadmap unveiled at the last IDF) power-tuned 65 nm-based processors at his keynote this morning. Here are a few tidbits:

1. The new CPUs are Woodcrest (server), Conroe (desktop), and Merom (mobile), based on a common micro-instruction core which combines the best of the NetBurst (Pentium 4) and Mobile (Pentium M) predecessors, and all touting EM64T 64-bit support.
2. Silicon for all three products is running very well. Otellini's presentation ran on a Merom-based notebook.Conroe was shown running 64-bit Fedora Linux, and Woodcrest ran Windows Server 2003.
3. Conroe will deliver a 5x performance-per-watt improvement over Northwood (the initial iteration of the Pentium 4).
4. Dempsey, Presler and Yonah, introduced at the Spring 2005 IDF, are also running and on 65nm. And two more single-core 65nm products are also running.
5. By Q3 2006, 65nm CPU shipments will exceed 90nm shipments. Also, by Q3 2006, dual-core CPUs will outship single-core CPUs. Over the next 18 months, 60 million dual-core processors will ship.
6. Looking beyond dual-core, over 10 quad-core and beyond projects are underway.

Otellini's presentation, which also covered a broad range of other topics, was followed by a more indepth press-only briefing given by Stephen L. Smith (VP of the Digital Enterprise Group) and David Perlmutter (VP and General Manager of the Mobility Group). I'll begin by providing links to a few of Smith and Perlmutter's foils:

• Revised CPU roadmap (note the new 65 nm products, and the four-plus core chips at the tail end of the decade)
• Single-to-multi-core transition forecast
• Intel's micro-architecture history
• Intel's next-generation architecture
• Intel's next-generation architecture (foil 2)
• Intel's next-generation architecture (foil 3) (particularly note the shared L2 cache, the L1-to-L1 cache direct communication link, and the dramatically shortened pipeline compared to the 20-stage pipeline in the first-generation 'Northwood' Pentium 4 and the 31-stage pipeline in today's 'Prescott' Pentium 4)
• One micro-architecture, three platform spins (note the common die between platforms, likely differentiated by clock speed and operating voltages)
• Platform timeline

A few bombshells from the presentation; all three of the new CPUs will be single-die dual-core configurations (unlike Presler, which will implement a dual-die, single package approach to 'dual core'). And none of these initial implementations of the new micro-architecture will support HyperThreading, although Perlmutter didn't rule out a resurrection of HT in the future.

• High-level specifications
• Architecture block diagram
• Multimedia-tailored enhancements over Dothan
• Yonah's Smart Cache
• Increasing performance while simultaneously reducing power versus Dothan
• The Sossaman spin of Yonah for blade and rack servers

Much speculation pre-show centered on whether or not the power-thrifty and clock-efficient Pentium M would be the foundation for Intel's next micro-architecture. I strongly suspected it would, and based on what I heard today I'm confident I was right. Simplistically, if you take Yonah, add a Pentium 4-like front-side bus, Virtualization Technology and other minor enhancements, and vary the L2 cache size.....you have Woodcrest, Conroe, and Merom.

Or at least that's what I think. Your thoughts? For more IDF coverage, see the usual suspects; AnandTech, Ars Technica, ExtremeTech, The Inquirer, The Register, etc...even MacWorld's here (for the first time)!