I was listening to Mentor Graphics’ CEO Wally Rhines’ keynote yesterday at the Globalpress event in San Francisco. He was discussing the state of IC EDA and I could not help but think of Bob Dylan’s new song Everything is Broken:

Broken lines, broken strings,
Broken threads, broken springs,
Broken idols, broken heads,
People sleeping in broken beds.
Ain't no use jiving
Ain't no use joking
Everything is broken.

Rhines always gives a good speech. Good because he infuses what he says with history and facts, not just opinions, slogans, and sales pitches. When Rhines says he’s a student of EDA history, you can believe him. When he says that the EDA tool that breaks most frequently is place and route, you can believe him. And that’s exactly what he said in his keynote speech, which focused on what’s broken in EDA as we move into the 45nm era.

“Engineers love innovation,” said Rhines. “They just don’t like to change their tool flows or learn new tools.” Consequently, they don’t change their tools very often. “Change only comes when the tools don’t work at all. That’s where we are with 45nm SOC design today.”

The first commercial place-and-route tool, said Rhines, appeared in 1984 just after the start of the 1-micron generation of ICs. These were the early days of gate arrays, when ASICs were just starting to become popular with system designers. This time also marks the start of the era of fabless semiconductor vendors. That same year, IC vendors rolled out the 0.75-micron generation of fabrication processes and the available place-and-route tools started to falter because of complexity. This first break provided an opening for Tangent’s router, which solved the routing complexity for “advanced” 0.75-micron chips. I remember Tangent Corp and Tangate, the routing tool that really made gate-array design possible for mere mortals. It was a very big deal back then. So big that Cadence acquired Tangent in 1989. By 1997, Cadence was selling $300 million worth of place-and-route IC tools per year for standard-cell IC design. A big deal for sure.

However, by 1997, we’d graduated from standard-cell ASICs to 0.25-micron SOCs. What’s the difference? SOCs contain microprocessors, which are really tough to route—especially around the critical general-purpose register file with its multiple read and write ports. The wheels fell off the gate-array-centric routers at that point and place-and-route tools were again broken.

About that same time, Gerry Hsu and several other Cadence employees left to form ArcSys, which developed a superior router that could successfully route the new 0.35/0.25-micron chips. ArcSys became Avanti! and was soon selling $300 million worth of place-and-route tools per year for the 0.18-micron generation of ASICs. Cadence then sued Avanti! for trade-secret theft and Avanti! eventually ended up as part of Synopsys, but that’s a different story. (A very interesting one, I might add.)

The next place-and-route crisis, at the 0.13-micron node, was caused by widespread failure of the existing tool flows to achieve timing closure. Enter Magma with a timing-driven place-and-route tool. By the time the 90nm IC node became established, Magma had become the place-and-route tool vendor of choice.

Now we’re at the 65nm and 45nm nodes and the wheels have again fallen off of the place-and-route tools. This time, says Rhines, process variability across a chip is the culprit. In addition, we’ve squeezed a lot of available margin out of designs. We push timing hard. Our designs are truly huge. We’ve reduced operating voltages to the point that 100mV or even 50mV of supply ripple cannot be tolerated. Meandering interconnect lengths are so long and vary so much from wire to wire and from layer to layer that critical paths abound.

We must now place huge constraints on chip designers. Where TSMC might have a design team sign off on four “corners” (temperature/voltage corner cases) for a 130nm SOC design and 10 corners for a 90nm design, it now requires signoff on as many as 21 corners for a 65nm design. That requirement represents a lot of design constraints. As a result, place-and-route tools are again “broken” because they are not designed for and cannot account for all of this variability. Existing tool vendors cannot fix their tools because it’s not possible through simple extension and the vendors must continue to support their existing customer base. That’s the reason that these broken tools are always replaced with new ones from startup EDA vendors (there’s a strongly implied invocation of Clayton Christensen’s Innovator’s Dilemma here).

Which leads us to the other tools in the design chain that are also broken at 65nm and 45nm. Functional-verification tools are “broken” because verification now consumes 50-70% of the SOC design effort. That’s huge and getting bigger. At this rate, said Rhines, functional-verification jobs would soon be available for “every man, woman, and child in India.” Although it’s nice to contemplate full employment for any country, this particular future is not economically viable and something will have to give.

What gives, says Rhines, is low-level ASIC design in the form of Verilog and VHDL. The abstraction level supported by these languages is too detailed for the design of chips with hundreds of millions of transistors. Rhines predicts that the era of system-level design using languages like System Verilog or VHDL with PSL (“property specification language” for assertion-based design) are the future. He also asserts that SOC designers will need to get a lot more serious about embracing pre-verified IP blocks (including embedded processors) for their designs.

Another factor breaking the tools is the need for better design of low-power systems. If the SOC design team fails to successfully design the chip because they can’t route it, achieve timing closure, or verify the design, then their company can’t ship the chip. If the design team succeeds in designing the chip but it draws too much power, their company will not be able to sell the chip. Both of these paths lead to product failure.

For far too long, SOC designers have been relying on RTL twiddling, circuit-design advances, and process tricks to alleviate the ills of unoptimized system architectures. “If you’re really after a low-power design,” said Rhines, “you must create a low-power design at the beginning. You have a big impact at the architectural level.” As the graph below shows, designers have far more control over system power at the architectural-design level, but they use precious few tools to explore alternative architectures to find power-optimized configurations. “Most of the EDA industry’s development has been far below the system level,” said Rhines. Unlike gate-level design, architectural design is still more craft than engineering.

The latest break at 45nm “will force people to use real system-level design tools,” said Rhines. The following graphic captures this situation nicely. Using RTL tools alone to explore a design space, the design team can only explore a small part of the space because RTL simulation takes a long time. There just aren’t enough days in a project to cast the exploration net widely. What’s needed is faster system simulation, which you can only get if you design at the system level rather than the gate level. That’s a more precise way of saying that you need to raise the level of design abstraction.

Rhines foresees much wider use of SystemC and other system-modeling and -simulation languages to develop complex SOC designs. “The algorithms are already written in C,” he said. “Simulate them in C.” I fully concur. Our opinions diverge when it comes to describing what will happen to that C code once the system is designed. Rhines believes the C code will be fed to a compiler and turned into hardware. No doubt he believes that because he’s the CEO of Mentor, which sells a tool called Catapult C that transforms C code into RTL hardware descriptions. On the other hand, I believe that much of that C code will be run on embedded processors tailored to the task at hand. After all, C is first and foremost a language designed to run on processors. No doubt my beliefs spring from my day job, working for a vendor that offers such processors. Rhines and I are both firm in our divergent convictions, so this seems like a very good place to end this blog entry.

(Note to other CEOs: If you want to see nice long blog entries about your keynote speeches, take a page out of Wally Rhines’ playbook. That guy can speak.)