Monday, October 22, 2007
Lithography crisis looms as the semiconductor industry squints at the 32nm half-pitch
Even as the semiconductor industry sees its first flickers of manufacturing activity at 45nm, process developers are looking ahead to the 32nm half-pitch—roughly, the 22nm logic process node. And they are not liking what they are seeing. Aside from the growing range of options and increasing uncertainty about the transistors that will be used at this node, and the growing complexity of the front-end-of-line process steps necessary to produce them, there is one giant crevasse yawning between here and there: the lack of any viable option for lithography.
It’s not for want of alternatives. Extreme ultra-violet (EUV), the euphemism for XRay lithography, was supposed to be ready to step into the breach by then. Just in case, very-high numerical aperture (NA) immersion with 193nm light was supposed to have been perfected by then, so that in a pinch it could be extended to the 32nm half-pitch. And double-patterning techniques with existing water-immersion lithographic equipment should have been familiar and ready to push to one more node in an emergency. But in one of those worst-case scenarios that spawn popular gift books, all three of these options have run into trouble.
The most obvious collapse has been the EUV program. There are presently only a couple of EUV steppers in the world. The two most obvious are at IMEC in Leuven, Belgium and at the nanoelectronics research center in New York. Last week at IMEC’s annual research review, it became apparent that the status of the ASML Alpha tool there was not encouraging.
The tool has been assembled and making patterns for some time now, but it is still very much a research project in its own right, according to IMEC executives. The tool is not ready to produce patterns of use to other programs within the semiconductor research cluster. “Setting the stepper up is not very straightforward,” admitted Luc Van der hove, executive vice president and chief operating officer of the research organization.
That turns the industry’s attention to the other major lithographic tool project, the advanced immersion stepper. By finding a liquid with an index of refraction much higher than that of water, and using it in combination with a very-high-index optical material, it is possible to create a 193nm optical column with an NA sufficiently high to meet the needs of the 32nm half-pitch. Unfortunately, the optical material has not been identified, and there are no known candidates for the fluid. So Ronse’s presentation warned that high-NA immersion lithography for the 32nm half-pitch will be at best late, and if it can be made to work at all it will only work for one generation.
With that second piece of bad news, all eyes turned to double-patterning technology. The good news here is that this, at least, is working, and can be done with the existing lithographic infrastructure. It is not easy, it adds a significant number of additional process steps to the front-end-of-line process, and it stresses—perhaps overstresses—overlay accuracy of the existing equipment. But this technique of dividing patterns into two or more separate masks, exposing, developing, cleaning, and etching them separately to produce one layer of features (see here) is at the moment the only game in town for 32nm half-pitch features.
There are limitations. In particular, splitting geometry into a pair of complementary masks is only a manageable mathematical problem for relatively regular patterns. It is not guaranteed to work for an area full of randomly-arranged features, such as often occur in cell-based logic designs. Spacer-defined patterning (see, for instance, here), a very clever approach that uses spacers and multiple etch steps to in effect multiply the number of lines in an area, shows great promise--but it only works for extremely regular patterns. So it appears that the only viable looking lithographic path to the 32nm half-pitch will demand the use of regular features, which in turn will impose upon designers the dreaded restrictive design rule regimen. (For a related discussion of RDR, see here.) I hope the EDA industry is keeping an eye on this.© Reed Business Information, a division of Reed Elsevier Inc. All rights reserved.
