Normally we think of ESL tools in terms of systems design at the stage where the partitioning between hardware and software is just beginning to solidify. Thus we want the tools to handle abstract behavior, some level of hardware abstraction, and compilable C++ all with the same level of agility. Of course we want the tools to provide us with a simulation of this virtual platform at nearly instruction-set simulator speeds, too. But a joint announcement by ESL tool vendor CoWare and microcontroller giant Renesas this morning illustrates that early system design is not the only way to use a system-level design environment. It can also be a software development tool.

Perhaps the way to put this announcement in perspective is to point out, as many others have previously, the fading of the distinction between high-end microcontrollers and application-specific standard products (ASSPs.) Companies like Renesas and NXP have created microcontrollers that, in their often-multicore processing power and complex memory architectures, in their use of application-specific accelerators, and in their complement of specialized peripherals, are almost indistinguishable from the kinds of SoCs created by vendors such as ST and even Broadcom.

As that distinction blurs and vanishes, a whole new light shines on hardware-software codesign tools. Originally, we thought of the tools as a solution to the problem that complex SoCs demanded close integration between hardware and software design teams, especially before the hardware entered the implementation phase. The tools allowed architects and implementers to explore algorithms, hardware/software partitioning, implementation strategies, and their implications for performance, power, and cost.

And according to Atsushi Hasegawa, executive general manager at the Renesas design and development business group, this concept now applies just as well to a high-end microcontroller development as it does to any other sort of SoC. Hasegawa said that Renesas used CoWare's tools to build high-execution-speed models of the company's SH-4A processor core, and of other cores used in some specific SH-4A-based microcontrollers. The main modeling process, Hasegawa said, took only about three weeks. He added that there are some accelerator cores in the family that presented much more difficult modeling problems. "We found modeling the CPU easy," Hasegawa explained. "But some of the accelerator cores execute 1,000 operations per clock cycle. It is not easy to build a model that will have high simulation performance with so much going on in the core."

But the company did not just have internal use in mind. Renesas and CoWare are teaming to make the tool and models available to Renesas microcontroller users as part of the users' software development environment. This will allow users to study, in particular, connectivity issues in their systems, as customers integrate models of their own hardware into the CoWare environment. So CoWare begins to extend its reach from an early-phase chip-and-firmware design tool into a software development environment for existing silicon.