On Friday, March 27, the IEEE CPMT (Components, Packaging and Manufacturing Technologies) local chapter in Austin, Texas, held an all-day workshop on 3D IC integration. The mixture of local speakers and invited speakers tried to present a coherent picture of where things are and where they are going in 3D. Pictured below are the morning speakers at the conference.

ADVERTISEMENT Morning workshop speakers included (left to right) Mike Shapiro, Bill Bottoms, Paul Franzon, Phil Garrou and Rao Tummala.

Before I comment on the technical content, let me say that it was depressing to see the 75% empty Freescale parking lot and hear from attendees that several of them were no longer employed by IBM or Freescale or TI. It was quite clear that the recession has hit this area full force. Here’s hoping that all of these technologists find suitable employment quickly.

Bill Bottoms heads up the ITRS packaging roadmap. The gist of his presentation can be summed up by one of his slides that read, “The 3rd dimension will be the key enabler (for the electronics industry to move forward) and supply chain maturity will determine the speed of adoption.” I couldn’t agree more.

Rao Tummala, whose Georgia Tech PRC (Packaging Research Center) is focused on 3D systems technology, made the point that 3D stacked chips are great, but eventually will need 3D systems in order to take advantage of the chip properties. They propose doing this on both silicon and non-silicon based interposers, which will be built to take advantage of the 3D chip's enhanced properties.

Mike Shapiro from the IBM Austin Systems and Technologies Group followed with a presentation on the IBM motivations and early applications for 3D. A key statement was that early on you cannot expect to save chip cost by using 3D technologies for their production, but rather cost savings would only show up at the systems level. Shapiro indicated that IBM is focused on developing a “rock solid” TSV process because they believe that the TSV yield must equal the interconnect yield on chip for eventual economics to make sense. He continued with his theme of “modularity,” which we discussed a few months ago (see PFTLE, "Highlights of 3D ASIP," Nov. 29, 2008).

Also of interest were his comments on the IBM-backed Nanoscale & Packaging Technology Center being put into upstate New York. IBM has agreed to invest $1.5B and the state of New York will invest $140M ($50M in 2009). Mike indicated that this program was proceeding despite the sluggish economic times. 3D integration technology is one of the main themes for this consortium. Shapiro indicates that IBM will be scaling up technologies that can be used to incorporate 3D technology into its products, which will take advantage of silicon interposers with TSV as shown in the slide below.

Source: IBM

Paul Franzon from North Carolina State discussed the advantages of 3D IC from the standpoint of complete chip redesign (reconfiguration), which, as you already know, I think is the ultimate goal of all 3D work. From all of his academic studies he has concluded that in general “3D IC buys you two generations of scaling.”

As further evidence that CMOS device performance has stopped improving, Franzon showed the MIT results that indicate that delay has actually begun the increase as we enter the 32 nm node (see figure below).

Beyond 40 nm, parasitic capacitances significantly impact transistor delay. (Source: A Khakifirooz, "The Future of High Performance CMOS: Trends and Requirements," 38th European Solid State Device Research Conf., September 2008.

For a specific radar FFT device that they are developing for a government agency in 3D IC technology, they have achieved:

• 60% decrease in memory power and a 5% decrease in logic power.
• 800% increase in memory bandwidth.
• 10% reduction in total silicon real estate.

Recall Franzon’s group at NC State is involved with the DARPA-sponsored Tezzaron Multi Project Wafer Program that we discussed a few blogs ago (see PFTLE, “Tezzaron Announces 3D IC Multi Project Wafer Program,” Feb. 2, 2009).

Vassilios Gerousis of Cadence presented “IC Design Challenges of Stacked Chip Using TSV,” which was met with great interest. As you know, I and a number of others have questioned why Cadence and the other big EDA tool vendors have not been more aggressive about the 3D market place. Gerousis indicated that Cadence is engaged with “leading commercial customers in 3D software development” and has developed a basic set of tools and a design methodology for 3D. Indications are that these tools are an extension of their current IC and SiP tools. In fact, we were told that Cadence had taped out two chips on a 45 nm process for its lead 3D customer in 2008. Great news and a strong indication that things are indeed moving ahead.

Professor Madhavan Swaminathan of the Georgia Tech PRC showed us the beginnings of some work he is doing to model the electromagnetic effects of TSV. Bottom line here is watch out for coupling due to signal leakage.

Before I finish, I should mention that I had an excellent dinner (Italian food, of course) and 3D discussion with Paul Ho (ex IBM’er currently of U Texas) who has entered the 3D IC technology arena. In the recent past, Paul and his group did some great work in the low-k area. He has now teamed up with my old friend and colleague Jay Im. I look forward to the team of Ho and Im producing some important research results in the 3D IC area in the next few years.

For all the latest in 3D IC integration, stay linked to PFTLE……………………