The problem of memory power management in an SoC has two components. First, the hardware hooks must be available to perform clock-gating, voltage reduction, and power-gating in order to attack both dynamic and static power consumption. But second, and just as important, the memory instance must be told when it is allowable to use its various power-saving modes. This is a non-trivial problem because many modes that go beyond simple clock-gating have significant entry-exit latencies and actually increase dynamic power during the entry and exit process. So without foreknowledge of circuit activity, it's neither safe nor rewarding to use these modes.

The result is often that designers, lacking detailed constraint data about memory use, tend to get conservative. They will only clock-gate the memory when the inputs can't change, and they often will use more aggressive power-down modes only at the block level, for instance when the entire SoC changes operating modes and will not use a functional block for a while. But conservative, while safe, wastes power.

Calypto Design announced yesterday that it has worked with Virage Logic to apply sequential analysis technology to the problem. PowerPro MG will examine the input logic to a memory instance and automatically generate additional RTL to improve the granularity of the signal applied to Virage's Memory Enable and Light Sleep pins. Then the company's SLEC tool will perform a formal equivalency analysis to demonstrate that the additional logic has not broken anything.

All of this is intended specifically to work with Virage's 40 nm SiWare memories. In addition to the usual Memory Enable pin, Virage has provided on these instances a Light Sleep pin that, Virage claims, reduces standby power by about half, while retaining data and outputs and offering a relatively fast return to normal operation. This is done, according to the company, by a combination of power-gating and source biasing within the instance. This is great news for leakage current, but it does create both energy issues, since it takes dynamic power to get in and out of the mode, and timing issues, since recovery is not instantaneous.

The results can be worthwhile, according to Calypto. Just how worthwhile will of course depend on the circuitry, operating modes, and use models of the particular design. But in a case study—presumably not one of the worst the company has seen—MG was applied to 14 memory instances. It was able to generate new enable signals for five of them, saving about 40 percent of the total memory dynamic power. And it was able to generate light-sleep signals for all 14 instances, reducing leakage in the memories by 55 percent. The result overall was a 40 percent reduction in memory power for the design, according to Calypto.

PowerPro MG works in series with PowerPro CG, and the same SLEC formal analysis pass can check the results of both tools. There is also a viewing tool so designers can see what MG is up to. Calypto CEO Thomas Sandoval said that the initial step with MG is this fully-automated approach. Down the road, the company hopes to use the tool not just to automatically generate new RTL, but to deliver hints to the architectural design team about how to give MG more room to work at the RT level. Also desirable, Sandoval said, was an ECO flow that would alert designers if an ECO had changed any of the conditions upon which the MG-generated RTL was based.