More and more design teams are taking a second look at the assumption that to go fast they need to be using the most advanced process available. Cost is one big incentive. But increasingly, risk of working in an advanced process, access to IP, and the difficulty of getting sufficient attention from the foundry for a leading-edge design are all additional factors. Finally, experience is beginning to suggest that for some designs, the performance advantage of going to the latest process may not be that great.

A case in point would be the Stream Processors Storm-1 media processing chip. Architecturally, the device is not unusual for its category, combining a pair of MIPS cores with an interesting 16-pipeline VLIW engine. But the specifications do catch one’s attention: the pipelines in the VLIW engine are running at 500 MHz in a strictly cell-based, 130 nm LV design.

The process choice and resulting performance come from a combination of circumstance and careful planning, according to Stream Processors vice president of silicon engineering Ted Williams. He says that the process choice had to be made two years ago, and was heavily influenced by perceived risk and by the availability of PHY IP that the company was in no position to engineer for itself. But in hindsight, he says, the choice couldn’t have been better.

The chosen 130 LV process operating at 1.0 V core voltage gave the team a combination of negligible leakage current, relatively low dynamic power and very good delay for lightly-loaded outputs. This was all the foundation the design team needed. Early on, the team looked at doing custom cell designs to get the most out of the process, but concluded that existing Artisan cell libraries and memory compilers would be sufficient.

The resulting chip pretty much speaks for itself. The VLIW unit has hit 800 MHz in the laboratory, and the company is rating it at 500 MHz for production. The two MIPS 4KEc cores, which were not subject to the same rigorous design and layout planning, run at 250 MHz. While the chip is not low-power by any means, it is efficient for its level of processing power, consuming 5 to 10 Watts to execute a high-performance software video encoder, for example. It is an interesting demonstration that in a fairly regular structure, careful design can get a great deal of performance out of a legacy process. Can a more regular approach, even at the loss of some processing efficiency, open up the option of using a far less expensive and less risky process? It’s a possibility that perhaps more design teams should consider.