IBM researchers have announced that they’ve found a way to use vacuum as the insulator on nanometer ICs. A self-assembling, nanotech polymer forms a hole-filled foam around the on-chip wiring. The nanotech involved mimics the structures nature uses to build seashells, snowflakes, and tooth enamel. The resulting structures have 20nm feature sizes and are much smaller than current photolithographic techniques can produce, which is why the nanotech is invoked.

Vacuum has a dielectric constant of 1. As low as you can go. According to IBM, the resulting vacuum insulation boosts chip speed by 35% or reduces energy consumption by 15%. Your choice. There’s the usual boilerplate about how this technique extends Moore’s Law in the press release too.

Note that air-gap construction isn’t new. GaAs chip vendors used it to produce fast chips back in the 1970s and 1980s, but the process was too expensive to use except for gold-plated military ICs. The new IBM process shoehorns well into existing CMOS fab lines. IBM’s use of nanotech gives this chip-construction technique another lease on life—IBM plans to use the fabrication technique for production chips in 2009. (More coverage on EDN's site here.).

Chip made with IBM’s nanotech air-gap technology