Thursday, December 18, 2008

IEDM: Micromirrors at IMEC reflect another path to maskless lithography


Everybody understands that mask costs are part of the problem in SoC design. Specifically, mask costs put a very high floor under the minimum volume for which you can afford to create a derivative design. Even if the incremental design and verification work is trivial, turning more than a few metal masks is out of the question unless the forecast volume is huge.

That limitation cuts into foundries' revenue, and so it is important to lithography equipment companies. And they are working on it. We have written previously about the work to eliminate contact and lower metal masks with direct-write e-beam systems. But quietly, lithography vendors are working in a different direction: digitally-controlled optical writing systems.

A hint at this work surfaced at the International Electron Devices Meeting this week in a paper by the European research consortium IMEC (the Interuniversity Microelectronics Center.) The paper described an 11 Mpixel silicon micromirror array fabricated on a relatively huge 10 cm2 die, over the top of an active 180 nm CMOS IC. The micromirror array, which has the largest pixel count reported to date, is intended for use in maskless lithography, and was developed for an unnamed lithography company (or companies.)  Compare it, for instance, to 2 Mpixle arrays built by Texas Instruments for consumer applications, and 5 Mpixel arrays for commercial cinema projection.

The idea is that by digitally controlling the tilt of each micrmirror in the array, it is possible to create an arbitrary light pattern that the optical column of a scanner can then focus onto the surface of a wafer. Of course 11 Mpixels is a tiny amount of information compared to all the data on a mask, but scanning an 11 Mpixel patch across the wafer, if the light is intense enough, is still going to be a lot faster than scanning the wafer with an electron beam.

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The device is interesting for several reasons beyond its potential application. First, as mentioned, the MEMS mirror array is fabricated on top of a standard CMOS wafer. IMEC buys the 200 mm wafers from an outside foundry and performs the processing to create the mirror array in-house. Second, unlike the TI arrays, which are made form a secret aluminum alloy, the mirrors in the IMEC process are polysilicon-germanium. It turns out that polySiGe, like the painfully-developed TI alloy, has very high durability: IMEC has tested the devices successfully at 1012 cycles.

Another interesting point about the array is that it represents a new business model for IMEC. In the past, the research organization has limited itself to what it calls pre-competitive research. IMEC chooses a question, assembles a syndicate of commercial companies who all need basic research on the question, and then does the research in partnership with the companies. The research phase ends and IMEC provides final results to the partners long before product development starts. But in this case, IMEC has used its own resources to do a product development.

"The industry maybe needs 50 to 100 dice per year of this device," explained IMEC department director Serge Biesemans. "There is no way that a commercial semiconductor company would be interested in this business. But it is feasible for us to design and manufacture the parts." So IMEC, in a strange way, finds itself drawn into the semiconductor manufacturing business, ironically, joining in the effort to reduce the minimum volume for new semiconductor designs.


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