In many ways this could be the year that Extreme Ultra-Violet (EUV) lithography happened at the SPIE conference. Sessions on the subject were packed, both with paper submissions and with attendees. An evening panel drew a similar crowd. And researchers reported solid results: patterns from IMEC, and plans for transistors from AMD. But it’s still not clear whether this is the year in which we first glimpsed the low-energy X-Rays at the end of the tunnel, or the year we first perceived the real scale of the problem.

First, the good news. IMEC and ASML reported progress with the so-called Alpha-Demo EUV tool in Belgium, including patterns that achieve approximately 35 nm resolution: nearly enough for a hypothetical 32 nm process node. And ASML is no longer the only game in town: both Nikon and Canon gave progress reports on their own tool developments. Meanwhile a joint paper by researchers from AMD, ASML, IBM, Mentor Graphics, Sony, and Toshiba America Electronic Components presented work that will lead to transistor-level devices using the ASML Alpha Demo tool in Albany, NY, for one of the mask layers. The rest of the layers will be done with conventional 193 nm lithography.

Then there’s the fine print. “We have momentum, but we are far from done,” said IMEC lithography department director Kurt Ronse. “Now we must do the infrastructure development.” The need for infrastructure comes in many areas, but Ronse says that three stand out in particular: resist, masks, and illumination.

Resist may be the primary limitation on EUV resolution at this point, according to Ronse. “There appear to be fundamental limits to the line-edge roughness we can achieve with chemically-enhanced resist technology, and they may limit their use below about 30 nm.” That, of course, would limit EUV tools to a resolution level already demonstrated by double-patterning with 193 nm immersion tools. There is a frantic search for alternatives going on, but at this point it is even unclear who will be funding the development. It may be too expensive a project for the resist suppliers to handle alone.

Further, there is the problem of repair, or rather of the impossibility of repair. EUV masks are built up from a number of reflecting, absorbing, and anti-reflection layers. Because there is no known way to patch holes in a layer, defects can only be repaired when they are on the surface of the stack. So repair appears to be much less of an alternative than it has been in the past. Finding a defect beneath the top layer pretty much means scrapping the mask. And defect densities are still nowhere near the necessary level for production.

Nor is that the only problem. Because of EUV’s tendency to be absorbed by nearly everything, EUV masks cannot have protective pellicles when they are in the optical column. So they are exquisitely sensitive to damage or defect-collection while in use. Papers at the EUV session looked extensively at contamination sources such as Carbon, and at techniques for zero-defect handling of the masks.

Then there is the matter of illumination. Ronse says that two alternative sources of EUV radiation are being explored now: discharge-based sources and laser-produced plasma sources. Unfortunately, today neither is within an order of magnitude of producing sufficient power for an early production tool. Worse, there are so many uncertainties in the roadmaps proposed by the numerous illumination vendors that skeptical researchers are asking for quantitative milestones and demonstrations at six-month intervals to verify that the sources are still on-track. That’s an indication of a worried industry.

Beyond this there are all the other infrastructure issues, including OPC algorithms that may become necessary at resolutions below about 20 nm. Right now, however, OPC is part of the good news: the previously-mentioned AMD paper reported that the data file for the EUV mask was only about ten percent the size of an equivalent data file for making a 193 nm mask, simply because no OPC decoration is necessary.