Anyone working at advanced IC geometries is familiar with the bad news: transistor leakage currents are going up, and intermetal parasitic capacitance is going up. Put the two together, and you have a really painful scenario for circuit designers. Ask for relief from process engineers, and you mostly hear “sorry, that’s physics.”

But a couple of announcements last week suggest that physics may not be as stubborn as most process engineers say. It may just demand some subtly. In particular, two separate teams announced very interesting results by using a different approach to dielectric film deposition.

Normally during the deposition process, you try to keep everything in the tool as constant as possible to avoid creating variations in the composition of the film. But it’s also possible, with minor changes to the tool or even just with changes to its controls, to intentionally vary the composition of a film during deposition.

Describing a paper at the International Electron Devices Meeting last week, NEC Laboratories (http://www.labs.nec.co.jp/Eng/index.html) chief materials researcher Yasunori Mochizuki described what the company calls density-modulated deposition as a key component of the interconnect stack the labs are developing for NEC’s 32 nm process. The problem that drove the research, according to Mochizuki, is that by 32 nm the insulating material between metal areas in the interconnect stack has become so thin that even at 1V—the lowest practical operating voltage for most circuits—electric fields are so strong that tiny dielectric defects cause breakdown.

The other work, by start-up Mears Technologies (http://www.mearstechnologies.com/) concerns control of transistor gate leakage current. In this case, the technique is once again varying the settings on a tool during deposition, but the material in question is epi, not low-k dielectric. (See a news story on the announcement here.) By varying the recipe during epi growth, the company creates what it calls a bandgap-engineered film: a material in which electron density varies along the Z-axis of the film. That leads, through quantum-mechanical wonders, to a film whose effective electron mass is greater along the Z-axis than along the length of the channel. And that impedes the flow of leakage current through the gate dielectric into the channel, without reducing the source/drain current. The result from a circuit designer’s point of view is a 60 to 80 percent reduction in gate leakage current at a given operating point, with no impact on other parameters, the researchers say.

Since there are no new materials involved, the idea is process-integration-friendly. The structure of the film is stable at processing and operating temperatures, and the technique appears applicable to heterogeneous orientations, strain-engineered films and other techniques on the roadmap.

So here are two illustrations that relatively simple tweaks to existing processes can make a big difference on just how high some of the hurdles on the semiconductor roadmap really are. As usual, the demise of Moore’s Law may have been somewhat hastily invoked.