Malaysian foundry Silterra is in a tricky position. As Peter Drucker pointed out many years ago, there is a right size for a company to be to exploit a particular opportunity. Too small, and the company simply can’t fund the development and risk necessary to serve the customers. Too large, and the company can’t afford the business, can’t manage it, or can’t react fast enough to find it.

It would appear that this notion certainly applies to the foundry business. We write all the time about the enormous capital investment required to put up a state-of-the-market foundry, and the enormous volumes—and substantial market share—required to service that kind of investment. It would sound from the numbers as if there is never going to be a foundry built again outside the inner circle of a few giant enterprises.

But clearly there’s something wrong with this argument. Here, for instance, is Silterra, quietly running their approximately 30K wafers/month operation, and planning not a graceful shutdown, but further capacity expansion. They are even doing joint development on 90 and 65 nm with IMEC. How could that make sense?

Not that complicated, explains the organization’s CEO, Eg Kah Yee. “It’s easy to fill a fab this size if you can find some spaces in the market where you can be number one or number two.”

Second, a little further out, according to Yee, a lot of chips with high-voltage circuitry will be migrating to 130 nm. High voltage, like precision analog, requires special structures, specific process controls and excellent modeling of parameters that a production CMOS logic fab doesn’t care much about. As these high-voltage chips, in areas like power management, actuators and sensors start to migrate away from their older processes, they become an opportunity for a specialty house like Silterra.

Similarly, step three is to be ready to capture the high-frequency RF designs that are currently in SiGe or other specialty RF processes with a cost-effective and well-modeled 130 nm RF CMOS process. And step four, really a part of all the previous steps, is to be extremely power-aware in creating the processes and libraries for each of these offerings.

That is really where the story gets interesting. The mature processes of today, including 90 and 65 nm processes, have left some important chips on the table, according to Yee. A process development effort today can achieve some things at a given geometry using discoveries that weren’t available to process developers even a year ago. One specific example—vital to both analog and RF CMOS—is flicker noise. “Flicker noise is primarily process-determined,” Yee says. “Everybody does things that help, including trying to manage interface states and junction purity. But we’ve recently had a breakthrough that proves process chemistry can have a major impact on flicker noise.”

A key component of making new processes—even breakthrough ones—into products is of course support: models, libraries and IP. Yee says that Silterra is working both with its growing internal expertise and with outside partners to ensure that when these analog, power, and RF designers do give the company a look, they will find the process knobs and IP they need waiting for them. “The first-tier customers just make us match their process specifications,” Yee explains, “but the second-tier customers want us to help port their design to our process.”