PCI Express gen-3, the 8 Gbit/s next generation of the successful serial bus standard, is still working its way through the definition process. It is now at revision 0.5. But already there is a rush to market, even though nothing is really finalized. Today Gennum's Snowbush IP division announced release of a 4-lane gen-3 PHY and accompanying endpoint/root/dual-mode controller block. The two IP blocks are available as GDS-II and RTL, respectively. The current implementation of the PHY is designed for TSMC's 40 G process.

Accompanying the Snowbush announcement, interface-chip specialist PLX Technology announced that they are using said IP in what is apparently the first gen-3 switch chip. So the vendors are off an running, before the standards committee even gets an integer digit on the revision number.

Getting that far out in front of a complex standard has its costs. "We don't expect to see rev 1.0 of the spec until Q1 of next year," said Snowbush director of sales Gary Ruggles. "So it was necessary to make the PHY design extremely configurable. We don't expect any huge changes, like changes in the 128b/130b encoding scheme, but there are likely to be minor shifts, and we need to be able to adapt quickly to them."

This has meant putting a lot of work into elasticity of the PHY design, as well as flexibility for the controller. The latter is a less serious issue, since it's easier to spin RTL for a new state machine, say, than to tear up custom-designed GDS-II and lay it back down.

In part, this was done by using a flexible H-bridge driver architecture in the transmitter. The transmitter design can shift energy into the precursor or postcursor portions of the signal without changing the overall power. On the receive side, the designers provide the usual linear equalizer, but also added a five-tap decision-feedback equalizer (DFE) block, designed to operate at quite low power levels. When it's not needed, the DFE can be switched into essentially a pass-through mode, bringing the power consumption to near zero. "Overall, the transmitter and receiver provide about 30 dB of total equalization," Ruggles said.

A good deal of thought went into debug capabilities as well. Of course the design is autocalibrating—pretty much a necessity for 10 Gbit operation in a 40 nm process. But it also provides some relatively advanced debug and test features, such as periodic jitter injection to test jitter margins, an analog test pad, an undedicated temperature sensor that the chip designer may use as she sees fit, and something of a Snowbush signature: an automatic eye-diagram generator.

A question that is still up in the air influenced the controller design. Along with adopting several innovations introduced in the 2.1 revision of gen-2, such as multicast and transaction-layer packet hints, the gen-3 controller will have a much richer set of power-reduction modes. Maybe. "The specification goes way beyond gen-2 in defining power states," explained Snowbush director of digital engineering Kishore Mishra. "Now there are 32 power states in active mode, allowing very close control of power consumption while the interface is running." The trouble is, the 32 states have not yet been defined. So the controller comes with a state machine to track the states, but as yet nothing connected to it.

Ruggles said that Snowbush has silicon for the 10 Gbit platform in house and running. "We have moved data between PHYs on Tyco and other backplanes successfully at 8 Gbits/s," he said.