The Electronic Component Technology Conference (ECTC) , is sponsored by the IEEE’s Component, Packaging and Manufacturing Technology Society (CPMT) and the EIA (Electronic Industry Association). For the Component and Packaging community this is the pre-eminent conference on such topics during the year. Their 59th annual meeting was held last week in San Diego. Despite the economy and H1N1 “pandemic” 520 paid attendees ( down ~ 25 % from last year) gave 262 oral and 74 poster presentations in 36 technical sessions. Unfortunately many of the speakers from Asia were not able to join us.

Demographically 42 % of the papers were from NA; 37% from Asia and 17% from Europe. 36% of the presentations were from Corporations and 64% from Academia. There were 52 exhibitors. Below we see General chair Rao Bonda (Freescale ) and Jean Trewhella (IBM) (next years General Chair) attending an awards ceremony.

While ECTC academic papers give good insight into what might be happening 5+ years out, I tend to focus my attention on the industrial presentations which offer insight into what may soon become commercial reality. 

STATS ChipPAC  focused on IPD technology. They  presented the (4) papers:

“Compact Balanced BandPass Filter for 3.3GHz – 3.9GHz WiMAX Applications”

“Design of Compact Power Divider Using Integrated Passive Device (IPD) Technology”

“Design of Optimal Coupled-Resonator Baluns in Silicon IPD Technology”

“Ultra-Wide-Band (UWB) Band-Pass-Filter Using Integrated Passive Device (IPD) Technology for Wireless Applications”

These are all based around the IPD technology they have been developing (shown below in cross section) with the help of Bob Frye of Rf Design Consulting. Some of you may recall  Bobs Rf work at Bell Labs during the MCM technology decade of the 1990’s. 

Amkor presented an innovative paper entitled, “Study of FCMBGA with Low CTE Core Substrates” which dealt with the flip chip packaging of large die  by incorporating a low CTE substrate core. In a large die FCBGA, underfill is usually placed between the die and substrate, to improve the fatigue life of solder bumps due to the thermo-mechanical stress induced by the CTE mismatch between silicon die and substrate. This conventional underfill package has several limitations with large die and large package applications. Capillary flow is usually slow due to the chip dimensions and could be incomplete, resulting in voiding under the die. Also, the process of capillary underfill restricts the space for passive component mounting besides the die due to underfill resin bleeding. 

Recent molding compound technology and equipment allowed the development of the "molded flip chip package" based on the transfer molding technology as shown in the figure below. This allows  underfilling of the die and passive component simultaneously during the molding process. The molding process is performed in a massively parallel configuration lowering process time and thus cost. ( their sister paper “Molded Underfill Development for FlipStack CSP” further discussed their molded underfill process)

In case of large die, especially > 15mm, commonly a heat spreader is required to meet JEDEC coplanarity specifications (< 8mil at room temperature). To meet large package coplanarity without a heat spreader, package coplanarity of FCMBGA was studied with various low CTE substrate core materials. A cross section of the package is shown below where the cross hatched region is the low CTE core. The substrate contained  4 thin core (400um thickness) layers. To compare warpage, different low CTE core materials were compared to standard core material.  Identity and CTE of the “low CTE” materials were unfortunately not presented.

Coplanarity at high temperature did not change significantly with low CTE substrate compared to standard substrates with heat sinks. Samples were subjected to level 3(L3) preconditioning with peak reflow temperature of 245 ºC, followed by -55ºC to 125ºC TC testing for  1500 cycles and all passed without any failures.

Cisco gave a half dozen presentations all relating to solder joint reliability giving a strong indication of where their R&D time has been spent recently.

Starting this weekend I’ll be covering new 3D IC information from the Conference. Then we’ll be looking at some technology updates from a few of the startups that we have been keeping an eye on: Alchimer, Replisaurus and Semprius.

For all the latest information on 3D IC and advanced packaging applications stay linked to PFTLE……………………………………………