For the most part analog designers have avoided the issues of sub-wavelength design-for-manufacturing (DfM.) Most chips with primarily analog content are done in large geometries—180 nm or larger—where issues such as lithography optimization, metal-density and pitch rules, and well-proximity effects are non-issues. Even when analog designers work on advanced-geometry SoCs, the tend to use very relaxed dimensions on analog circuitry, avoiding the need to worry about DfM.

But all that is changing, according to Tom Wong, vice president of business development at DfM tool vendor Takumi Technology. A combination of factors is pushing analog designers inexorably toward smaller geometries, and into the waiting jaws of DfM troubles. And unlike in purely digital designs, where the penalty for ignoring DfM may be poor yields, the analog designer may pay with circuits that look correct but perform irretrievably out of spec.

One of these driving factors is simply the need for performance. For RF designers, 65 and 45 nm transistors offer undreamed-of cut-off frequencies and can be remarkably low-noise. If you have to do multi-GHz RF in CMOS, working with minimum-dimension transistors in an advanced geometry may be your only realistic choice. Similarly, the lower voltages available in advanced processes promise significant power savings, if you can afford the reduced noise margins. Another pressure comes from economics. It's OK to work at relaxed geometry when your little analog block is taking up 10 percent of a die in a 180 nm process. But when all the digital circuitry in the SoC has shrunk and you are taking up half of the die at 40 nm with the same function, management may be less understanding of your taste for really big transistors.

It might seem reasonable that, since analog circuits are hand-crafted anyway, analog designers could just craft around the known issues in fine geometries. But Wong warned that the issues now appearing in analog designs aren't necessarily obvious enough to anticipate. "For instance at 65 nm, issues seem to show up first in device matching," Wong said. "You layout two transistors that are mirror-images of each other and expect them to be matched. But after placement, well-proximity effects can leave you with two identical transistors that have quite different current characteristics." Asymmetry of the two transistor channel regions with respect to surrounding wells will mean that the two channels are under quite different strain, and hence have quite different carrier mobilities.

Digital designers can dodge many of these issues by confining them to the level of cell design. If the cell library is done carefully, at least in the 90-65 nm region, then most of the nasty issues will not appear for the chip-level designer. But there is no such simple barrier between cell design and circuit layout in the analog world. It's not clear that DfM-optimized p-cells, even if such a thing is possible, would lead to optimized-by-construction circuits.

Just what sort of circuit optimization analog designers want is still an issue, however. Wong said that many analog designers are still very reluctant to accept anything that smacks of automated layout. They want a DfM tool to scan their design and advise them of possible rule violations, variability sensitivities, or yield issues. They don't want the tool going in and proposing fixes. But as the number of potential issues rises and the number of failure mechanisms that designers must consider increases, a tool that scans your layout and reports that you've done it all wrong may be less than ideal. Add to this the fact that circuits are getting more complex in order to compensate for the problems with minimum-dimension transistors. Analog circuits with thousands of transistors are not uncommon already. At some point, even master analog designers may have to accept some automated layout optimization.