A start-up making its initial public announcement today could easily escape the notice of busy chip designers. DFMSim is one of those companies, spawned by the gradual dissolution of the wall between physical design, process engineering, and process control, that is almost impossible to classify. Yet DFMSim's work could have significant long-term implications, and some short-term benefits as well, for physical designers.

To offer too crude a characterization, DFMSim makes specialized data-mining tools to help process engineers extract patterns from the fire hose of manufacturing data coming out of the wafer-processing equipment. Their initial products, already in use in a small number of fabs, include a toolkit for analyzing overlay accuracy in the lithographic equipment, and a similar toolkit for analyzing critical-dimension (CD) data coming out of metrology. A future release will add a toolkit for resist analysis that will be able to analyze the settings and results on the steps that come after exposure—development, cleaning, etch, stripping, etc.

These tools fit within a more complex framework of software. The framework as a whole acts to collect data from the various tools—the stepper, metrology tools, and eventually etch and other stations—transform the coordinate systems used by each individual tool into a common wafer coordinate system, and filter the data to make apparent the patterns that the process engineers need to see.

The tools are separate modules that plug into a tool backplane. Plug-in tools can accept and transform data from a specific piece of process equipment, or they can perform a particular kind of analysis. The environment includes a high-performance simulation engine and an analysis engine, so that DFMSim not only collects and preprocesses the data, but it analyzes the results and does process simulations based on the measured data.

The short answer is that by using the DFMSim tools, process engineers can isolate systematic variations—such as a problem in data preparation that is causing consistent overlay errors in lithography, and hence degrading CDs—and act to reduce them. This process of hunting down and reducing sources of variation can make a huge difference to chip designers, by reducing the standard deviations of parameters in the process's device models. Less variations in CDs can mean less performance given up to guardbanding—even with statistical timing analysis.

The longer answer has to do with design tool evolution. The major EDA companies have been saying for some time now—and they are starting to put prototypes where their mouths are—that physical design tools can't do their job at 40 or 32 nm based solely on design rules. The tools have to be model-based. But that means the foundry has to provide fast, accurate process models to their customers to plug into the EDA tools. Both fast and accurate are issues here.

Fast is a problem because the source of these models right now is the Process Compact Models (PCMs) used by the foundries in process simulation (PCAD.) The PCMs may be compact, but they are nowhere near compact enough to run inside a routing tool, for instance. So the EDA vendors and process engineers are working together to extract mini-models from the PCMs. In doing this, it's vital to have a simulation environment that gives you some idea of the errors you are causing by your abstraction.

The accurate part is also an issue. As DFMSim CEO Anantha Sethuraman points out, the PCMs themselves are based not on hard data, but on a simulation using parameters that are in turn based on a simulation. The goal of DFMSim's tool is to replace these equation-based empirical models with hard process data from real wafers—in effect, creating a data-based model of all the systematic yield mechanisms in the process. That data could in turn be coded into the PCMs and encrypted, then passed to the EDA tools. The result would be model-based EDA tools using not empirical equations but reductions of actual equipment data loggings to perform their jobs. That would be another significant step forward.

But this is in the future. Today, DFMSim is selling a set of tools specifically for process engineers—and primarily process engineers in IDMs—that will be invisible to design teams. Still, it's a good idea to know what's cooking behind the curtain.